AN2364 Freescale Semiconductor / Motorola, AN2364 Datasheet - Page 11

• Manufacturer Part Number: AN2364
• Description: Using the Table Stepper Motor TPU Function (TSM) with the MPC500 Family
• Manufacturer: Freescale Semiconductor / Motorola

4.1.11 HSQ0
Host sequence bit 0 on the master channel is used to select the type of acceleration parameter table. If HSQ0
= 0, then the local table configuration is selected. If HSQ0 = 1, the split table configuration is selected.
HSQ0 should be initialized by the CPU prior to issuing the first move request HSR and should not be
changed while the motor is running.
4.1.12 HSQ1
Host sequence bit 1 on the master channel is used to select the number of rotates of PIN_SEQUENCE
between slave channels. If HSQ1 = 0, then one rotate is performed. If HSQ1 = 1, then two rotates are
performed. HSQ1 should be initialized by the CPU prior to issuing the first move request HSR and should
not be changed while the motor is running.
5
This section provides information concerning the TPU host interface to the TSM function.Figure 5 is a TPU
address map. Detailed TPU register diagrams follow the figure. In the diagrams, Y = M111, where M is the
value of the module mapping bit (MM) in the system integration module configuration register (Y = 0x7 or
0xF).
MOTOROLA
Host Interface to TSM Function
$YFFE00
$YFFE04
$YFFE06
$YFFE0A
$YFFE16
$YFFE18
$YFFE1C
$YFFE1E
$YFFE20
$YFFE24
$YFFE26
$YFFE02
$YFFE08
$YFFE0C
$YFFE12
$YFFE14
$YFFE1A
$YFFE22
$YFFE0E
$YFFE10
Address
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Using the Table Stepper Motor TPU Function
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0
DEVELOPMENT SUPPORT STATUS REGISTER (DSSR)
DEVELOPMENT SUPPORT CONTROL REGISTER (DSCR)
CHANNEL FUNCTION SELECTION REGISTER 0 (CFSR0)
CHANNEL FUNCTION SELECTION REGISTER 2 (CFSR2)
CHANNEL FUNCTION SELECTION REGISTER 3 (CFSR3)
TPU INTERRUPT CONFIGURATION REGISTER (TICR)
CHANNEL FUNCTION SELECTION REGISTER 1 (CFSR1)
TPU MODULE CONFIGURATION REGISTER (TPUMCR)
CHANNEL INTERRUPT ENABLE REGISTER (CIER)
DECODED CHANNEL NUMBER REGISTER (DCNR)
CHANNEL INTERRUPT STATUS REGISTER (CISR)
HOST SERVICE REQUEST REGISTER 0 (HSSR0)
HOST SERVICE REQUEST REGISTER 1 (HSSR1)
Figure 5. TPU Address Map
SERVICE GRANT LATCH REGISTER (SGLR)
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CHANNEL PRIORITY CHANNEL 0 (CPR0)
CHANNEL PRIORITY CHANNEL 1 (CPR1)
HOST SEQUENCE REGISTER 0 (HSQR0)
HOST SEQUENCE REGISTER 1 (HSQR1)
TEST CONFIGURATION REGISTER (TCR)
LINK REGISTER (LR)
TSM Function Parameters Address Maps
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