AN2405 Freescale Semiconductor / Motorola, AN2405 Datasheet - Page 11

• Manufacturer Part Number: AN2405
• Description: Supplemental Information for LCD Interfacing for the MC9328MX1 Application Processor Application Note
• Manufacturer: Freescale Semiconductor / Motorola

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6.1
For SDRAM access, a fixed burst length of 8 is preferred.
For a heavily loaded bus and SDRAM access, a dynamic burst length is recommended.
6.2
The LCDC output data rate is determined by:
Refresh Rate—The refresh rate is determined by the panel specification. For a TFT panel typical refresh rates are
around 60 frames/sec.
For example:
The required data output rate:
If HCLK (DMA CLOCK) is running at 96 MHz, then the maximum data rate is:
Therefore, the theoretic bandwidth used by the LCDC = 73 / 3072 = 0.023
In a customer’s application data under-run may occur due to heavy bus loading as well as a priority issue with the
memory controller. To detect a data under-run event, the user can perform the following:
Freescale Semiconductor
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Other Considerations
bit per pixel
panel size
240
refresh rate at 60 Frame/sec.
240
32
Read the Under-Run bit in the LCDC status register to see if it is set.
Monitor the period of HSYNC/VSYNC to see if it is changing intermittently.
LCDC DMA Setting
Bandwidth and Detection of LCDC Under-Run
×
×
×
96 M = 3072 M bit /sec.
320 TFT panel 16 bpp color
320
×
i.MX Supplemental Information for LCD Interfacing Application Note, Rev. 1.1
16
×
60 = 73 M bit/sec (approximately)
Fixed burst length
Fixed burst length
Table 7. Dynamic Burst Length Settings
Table 6. Fixed Burst Length Settings
High mark
High mark
Low mark
Low mark
Item
Item
DMA Register Setting
DMA Register Setting
1
8
4
0
8
3
Other Considerations
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