AN2408 Freescale Semiconductor / Motorola, AN2408 Datasheet - Page 2

• Manufacturer Part Number: AN2408
• Description: Examples of HCS12 External Bus Design A Companion Note to AN2287/D
• Manufacturer: Freescale Semiconductor / Motorola

Example #1 — Byte-Wide SRAM Interface (Narrow Mode) ECLK Gated
Precepts
These precepts apply to all the following examples:
Example #1 — Byte-Wide SRAM Interface (Narrow Mode) ECLK Gated
The following schematic is one of the simplest examples of HCS12 interfacing. A small 8-bit wide SRAM
device is attached to the external bus in expanded narrow mode. This SRAM device could represent the
interface of other devices with small memory-mapped or byte-oriented I/O.
Comments:
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In some of the designs, there is no data buffer. These designs assume that the VOH levels of the
external device match those of the MCU. Do not attempt to use resistive pull-up devices on a
fast high-capacitance bus to match I/O levels. With high-speed static memories, a data buffer
may be required to interface with a 5 V powered MCU. Verification of the external device’s VOH
levels is required. Lower voltage MCUs may not require a bus buffer. High-speed SRAM with
tEHOZ < 8 ns must be used to ensure that the SRAM bus is three-state prior to the next MCU
address drive.
The MCU reset signal is not gated with the SRAM selects. This does not present a problem in these
designs because the external bus (and consequently the external device) will be “off line” during
reset. During the power-up sequence, external devices may become active before the MCU. In
some modes, the MCU’s ECLK will start up prior to the release of reset while the R/W signal is still
low, causing external memory corruption. Some designs, especially emulation systems, may
require gating with reset.
There will be occasional bus contention in these designs if the IVIS bit in the MODE register is set,
as the NOACC signal is not implemented. Any MCU “free” cycle preceded by a data fetch could be
interpreted as a valid external read access by the SRAM. Though this will not corrupt external
memory, it will increase power consumption.
Address decoding is implemented to ensure writes to replaced ports (A, B, E, K) and their
configuration registers do not corrupt SRAM locations. Errant writes to these registers will be
echoed externally for possible port replacement and may cause external memory corruption. If
software is configured to protect against errant accesses, the decode is not necessary.
It is assumed that the memory area from $4000–$7FFF is clear of internal FLASH by setting the
ROMHM bit in the MISC register.
The active-high chip-enable signal that is available on these low-density SRAMs is important to the
design, because the ECLK signal is used as the enable to signal the completion of access to the
SRAM. If MCU signals that are gated with logic are
these gated control signals negate, causing SRAM data corruption.
The ‘374 type latch and the SRAM access speed will require at least one additional MCU clock
stretch to access these devices or reduced MCU speed.
Memory is available from $4000–$5FFF.
Examples of HCS12 External Bus Design, Rev. 2
used,
the MCU data may be released before
Freescale Semiconductor