AN2502 Freescale Semiconductor / Motorola, AN2502 Datasheet - Page 16
AN2502
Manufacturer Part Number
AN2502
Description
Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
1.AN2502.pdf
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AN2502/D
16
Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
After the parity bit is transmitted, one or two stop bits are transmitted depending
on the
Freescale Semiconductor, Inc.
Figure 25
For More Information On This Product,
SB
IN THE LAST BIT TRANSMISSION,
THE CHANNEL IS CONFIGURED AS
SET-ON-OUTPUT-COMPARE
TO SEND STOP BIT.
bit in rSCSR1.
Go to: www.freescale.com
shows the timing for parity bit transmission.
1.
TPTY
parity bit.
TPTY
Figure 27. Transmission of Stop Bits
LAST DATA BIT
OR PARITY BIT
Table 6. Parity Bit to be Transmitted
Table 7. Stop Bits to be Transmitted
0
0
1
1
Figure 26. Parity Bit Transmission
1 BIT-TIME
SB
(1)
1
0
bit is used for temporal computation of the
DATA BIT
LAST
PTY
0
1
0
1
Stop Bits to be Sent
STOP BIT
FIRST
Two stop bits
One stop bit
Parity Bit to be Sent
PARITY BIT
AFTER THE STOP BIT IS SENT,
THE CHANNEL IS TURNED OFF
IF SCTE FLAG IS CLEAR.
IF SCTE IS SET, THE CHANNEL IS
CONFIGURED AS
CLEAR-ON-OUTPUT-COMPARE
TO SEND THE NEXT START BIT.
1
0
0
1
STOP BIT
SECOND
MOTOROLA
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