AN2519 Freescale Semiconductor / Motorola, AN2519 Datasheet - Page 5

• Manufacturer Part Number: AN2519
• Description: 3Sin with Dead-Time Correction - XOR version TPU Function Set
• Manufacturer: Freescale Semiconductor / Motorola

Detailed Function Description
3-Phase Sine Wave
Generator with
Dead-Time
Correction – XOR
version – R channels
(3SinDtXor_R)
and 3-Phase Sine
Wave Generator with
Dead-Time
Correction – XOR
version – T channels
(3SinDtXor_T)
MOTOROLA
NOTE:
3Sin with Dead-Time Correction – XOR version TPU Function Set (3SinDtXor)
A CPU routine that configures the TPU can be generated automatically using
the MPC500_Quick_Start Graphical Configuration Tool.
The 3SinDtXor_R and 3SinDtXor_T TPU functions work together to generate
6 pairs of XOR gate inputs. The XOR gate outputs then produce a 6-channel
3-phase center-aligned PWM signal with dead-time between the top and
bottom channels. In order to charge the bootstrap transistors, the PWM signals
start to run 1.6ms after their initialization (at 20MHz TCR1 clock). The functions
generate signals corresponding to Reference Voltage Vector Amplitude of 0
(50% duty-cycle) until the first reloaded values are processed.
The CPU controls the PWM output by setting the TPU parameters. The Stator
Reference Voltage Vector Amplitude Ampl, the Stator Reference Voltage
Vector angle Theta (32-bit) and the angle increment dTheta (32-bit), can be
adjusted during run time. The PWM period T and the prescaler – the number of
PWM periods per reload of new values – are also read at each reload, so these
parameters can be changed during run time. Conversely, the dead-time (DT) is
not supposed to be changed during run time. The phase currents currentA,
currentB and currentC are read by the TPU asynchronously to the PWM
parameters reload. They are read in the last part of the edge-time calculation
to reflect the latest state of the phase currents. The CPU notifies the TPU that
the new reload values are prepared by setting the LD_OK parameter. The TPU
4. Issues an HSR (Host Service Request) type %10 to one of the
5. Enables servicing by assigning a high, middle or low priority to the
Freescale Semiconductor, Inc.
For More Information On This Product,
3SinDtXor_R channels to initialize all 3SinDtXor_R and 3SinDtXor_T
channels. Issues an HSR type %10 to the 3SinDtXor_sync channel,
3SinDtXor_res channel and 3SinDtXor_fault channel, if used.
channel priority bits. All 3SinDtXor_R and 3SinDtXor_T channels must
be assigned the same priority to ensure correct operation. The CPU
must ensure that the 3SinDtXor_sync or 3SinDtXor_res channels are
initialized after the initialization of 3SinDtXor_R and 3SinDtXor_T
channels:
–
–
–
assign a priority to the 3SinDtXor_R and 3SinDtXor_T channels to
enable their initialization
if a Synchronization Signal or a Resolver Reference Signal channel
is used, wait until the HSR bits are cleared to indicate that
initialization of the 3SinDtXor_R and 3SinDtXor_T channels has
completed and
assign a priority to the 3SinDtXor_sync or 3SinDtXor_res channels
to enable their initialization
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Detailed Function Description
AN2519/D
5