AN2539 Freescale Semiconductor / Motorola, AN2539 Datasheet

AN2539

Manufacturer Part Number

AN2539

Description

Using the MC9328MX1/MC9328MXL Single Internal 32.768 kHz Crystal to Generate System Clock and USB

Manufacturer

Freescale Semiconductor / Motorola

Datasheet

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Application Note

AN2539/D

Rev. 0, 05/2004

Using the MC9328MX1/

MC9328MXL Single

Internal 32.768 kHz

Crystal to Generate

System Clock and USB

By: Walter Law

Contents

Introduction. . . . . . . . . . . . . 1

Measurement Setup . . . . . . 1

Measurement Results. . . . . 2

USB Certification Results . 3

Conclusions . . . . . . . . . . . . 4

Appendix . . . . . . . . . . . . . . . 4

This document contains information on a new product. Specifications and information herein are subject to change

1 Introduction

The MC9328MX1 and MC9328MXL (i.MX) processors USB module contains a single

internal 32.768 kHz crystal used by both the MCU PLL and System PLL for system clock

generation. This document contains jitter measurement results using this single internal

32.768 kHz crystal to generate not only the MCU PLL and System PLL system clock, but the

48 MHz USB clock as well.

The 48 MHz USB clock is usually generated by an external 16 MHz crystal input to the

System PLL. However, to save space and cost, the 48 MHz USB clock can also be generated

by the single internal 32.768 kHz crystal.

The jitter generated by both inputs is measured independently and as of this publication date,

the jitter measurement results meet USB Specification (Revision 1.1). The results show full

speed jitter requirements using the single internal 32.768 kHz crystal to generate the 48 MHz

USB clock. The USB certification results are provided at the end of this document.

2 Measurement Setup

The 48 MHz clock for the USB module in the i.MX processors is output to the CLKO pin by

writing 0x010 to the CLKO_SEL bits [31:29] of the Clock Source Control Register. A

Tektronix TDS7404 digital oscilloscope was used to measure the clock jitter from the CLKO

pin on the i.MX Application Development System board (ADS).

The 48 MHz USB clock can be generated by either an external 16 MHz crystal input to

System PLL, or by the single internal 32.768 kHz crystal. Independent measurements of

USB clock jitter were taken using the external 16 MHz crystal as the source and the internal

32.768 kHZ crystal as the source to the System PLL.

The Clock Source Control Register settings that force output of the 48 MHz USB clock to

CLKO pin and for selecting either the internal 32.768 kHz crystal or the external 16 MHz

crystal for System PLL are shown in Table 1.

Freescale Semiconductor, Inc.

For More Information On This Product,

Crystal Source for System PLL

Table 1. Clock Source Control Register Settings

Go to: www.freescale.com

32.786 kHz

16 MHz

0x4700AC03

0x4743AC03

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