AN2667 Freescale Semiconductor / Motorola, AN2667 Datasheet - Page 6

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AN2667

Manufacturer Part Number
AN2667
Description
Multi-Controller Hardware Development for the MPC5xx Family
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
accesses therefore only 3 slaves are allowed in the system. The only possible way to
use more than four devices (1 Master & 3 Slaves) in the system is to configure up to an
additional four devices as masters that do not allow any other master to access their
internal address space. Another reason for having different internal memory maps is
that each controller is allowed to have its own interrupt handlers and reset routines.
In any case, the maximum capacitance of bus and clock signals should not exceed the
value stated in the electrical specification for this family of devices.
e.g. In a dual controller system the master device could have its base address at 0x0 by
setting IMMR[ISB0:2] = 0b000 and the slave device could have its base address at
0x400000 by setting IMMR[ISB] = 0b001.
3.3
Each controller can be programmed as a Master, Slave or Peripheral device by
configuring the EMCR[PRPM] (peripheral mode bit) and EMCR[SLVM] (slave mode bit)
in the following manner:
MOTOROLA
• Master Mode (Default)
How is Master/Peripheral/Slave Mode selected?
From reset master mode is selected by default on all members of the MPC5xx
family. The pertinent bits which control this functionality are EMCR[PRPM] = 0 &
Figure 3.2 MPC5xx Internal Memory Map
Multi-Controller Hardware Development for the MPC5xx Family
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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