AN2768 Freescale Semiconductor / Motorola, AN2768 Datasheet - Page 11

• Manufacturer Part Number: AN2768
• Description: Implementation of a 128-Point FFT on the MRC6011 Device
• Manufacturer: Freescale Semiconductor / Motorola

The imaginary (or sine) part of the twiddle factors is stored immediately after the real (or cosine) part of the
twiddle factors. Each part of the twiddle factors has an associated pointer that is updated during the butterfly
operations only when the frame buffer offset exceeds the limit of addressability of the instruction, which is 64.
3.3 Transposition for Bit Reversal
The bit reversal of 128 complex input data requires two 128-element transpositions. Each 128-element
transposition has two simultaneous 64-element transpositions on the top and bottom rows of the RC array. The
transposition is performed for the 128 real numbers and then for the 128 imaginary numbers. The steps in the
transposition are as follows:
Before the transposition begins, circular buffer 0 is selected and initialized to point to the beginning of the input
data in the frame buffer so that data can be loaded into the RC registers without incurring pointer updates. The code
for circular buffer set-up and consecutive frame buffer row loading is listed in Example 1.
Freescale Semiconductor
1.
2.
3.
4.
5.
Set up circular buffer 0.
Load 64 real numbers into the R0, R4, R2, R6, R1, R5, R3, and R7 registers of the first row of RCs in
the array.
Load the next 64 real numbers into the R0, R4, R2, R6, R1, R5, R3, and R7 registers of the second row
of RCs in the array.
Transpose both rows to shuffle the 128 real numbers:
R0–R7 → R8–R15
R0–R7 → R0–R7
Push the G5–G8 data to the frame buffer and reshuffle the G1–G4 data for the butterfly.
_DEC_CIRCULAR_BUFFER_SELECT = 0;
_DEC_AUTOINCREMENT0 = (unsigned long)psiFBInputData;
MORPHO_ASM( psiFBInputData )
Example 1. RCF Circular Buffer Initialization and Frame Buffer Row Loading
/** LOAD INPUT DATA **/
/***** Row0 *****/
/* Load input data(Re0-63)*/
CELL{0,*}:OUT_REG R0=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{0,*}:OUT_REG R4=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{0,*}:OUT_REG R2=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{0,*}:OUT_REG R6=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{0,*}:OUT_REG R1=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{0,*}:OUT_REG R5=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{0,*}:OUT_REG R3=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{0,*}:OUT_REG R7=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
/***** Row1 *****/
/* Load input data(Re64-127)*/
CELL{1,*}:OUT_REG R0=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{1,*}:OUT_REG R4=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{1,*}:OUT_REG R2=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{1,*}:OUT_REG R6=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{1,*}:OUT_REG R1=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{1,*}:OUT_REG R5=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{1,*}:OUT_REG R3=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
CELL{1,*}:OUT_REG R7=BYP{FB++{16,OMEGA_RT, COL_BUS, WORD}};
Implementation of a 128-Point FFT on the MRC6011 Device, Rev. 0
The FFT on the MRC6011 Device
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