AN2798 Freescale Semiconductor / Motorola, AN2798 Datasheet - Page 8

• Manufacturer Part Number: AN2798
• Description: Migrating from the MPC855T to the MPC885
• Manufacturer: Freescale Semiconductor / Motorola

New Features for MPC885
6.2 Digital Phase Lock Loop
The MPC885 features a digital phase lock loop (DPLL). The main purpose of the DPLL is to generate a stable
reference frequency by multiplying the frequency and eliminating the clock skew. The DPLL allows the processor
to operate at a high internal clock frequency using a low frequency clock input, providing two advantages. First,
lower frequency clock input reduces the overall electromagnetic interference generated by the system. Second, the
programmability of the oscillator enables the system to operate at a variety of frequencies with only a single external
clock source. To ease the transition from the MPC855T phase lock loop (PLL) to the DPLL, a tool that calculates
DPLL settings is available on the MP885 Product Summary Page at www.freescale.com. The major migration
concerns regarding the DPLL are as follows:
For a detailed description of these items, please refer to the MPC885 PowerQUICC Family Reference Manual.
6.3 Security Engine
The block diagram of the security engine’s internal architecture is shown in
module is designed to transfer 32-bit words between the MPC8XX bus and any register inside the security engine
core.
An operation begins with a write of a pointer to the crypto-channel fetch register, which points to a data packet
descriptor. The channel requests the descriptor and decodes the operation to be performed. The channel then asks
the controller to assign crypto execution units and fetch the keys, IVs, and data needed to perform the specific
operation. The controller assigns execution units to the channel and makes requests to the master interface to satisfy
the requests. As data is processed, it is written to the individual executions unit’s output buffer and then back to
system memory by means of the MPC8XX I/F module.
The internal registers for the security engine can be accessed when IMMR [ISB]14:15 = 10. The MPC885
PowerQUICC Family Reference Manual lists details of the registers and their locations in the internal memory map.
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The input clock requirements are different
The configuration of MODCK[1-2] has changed
DPLL does not start to lock until the negation of POREST has occurred
MPC8XX
Bus I/F
Migrating from the MPC855T to the MPC885, Rev. 0
Figure 6. Security Engine Functional Blocks
Unit
Controller
Crypto-
Channel
DEU
FIFO
FIFO
AESU
Figure
6. The MPC8XX bus interface
MDEU
FIFO
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