SSD1789A Solomon Systech, SSD1789A Datasheet - Page 19

• Manufacturer Part Number: SSD1789A
• Description: CSTN LCD Driver
• Manufacturer: Solomon Systech

www.DataSheet4U.com
7
7.1
The Microprocessor Interface unit consists of three functional blocks for driving the 6800-series parallel interface, 8080-
series parallel interface, 3-lines serial peripheral interface and 4-lines serial peripheral interface. The selection of different
interface is done by PS2, PS1 and PS0 pins. Please refer to the pin descriptions on page 16.
Figure 3 - Read Display Data
SSD1789A Series Rev 1.0
DATA BUS
a)
b) MPU Parallel 8080-series Interface
c)
FUNCTIONAL BLOCK DESCRIPTIONS
E( RD )
R
Microprocessor Interface Logic
/
MPU Parallel 6800-series Interface
The parallel Interface consists of 16 bi-directional data pins (D15 – D0),
high indicates a read operation from the Graphical Display Data RAM (GDDRAM) or the status register.
input low indicates a write operation to Display Data RAM or Internal Command Registers depending on the
status of
refer to Figure 17 to Figure 19 for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to
match the operating frequency of the GDDRAM with that of the MCU, some pipeline processing is internally
performed which requires the insertion of a dummy read before the first actual display data read. This is shown
in the following diagram.
The parallel interface consists of 16 bi-directional data pins D
serves as data read latch signal (clock) when low provided that
from GDDRAM or reading the status from the status register is controlled by
write latch signal (clock) when low provided that
writing the command to the command register is controlled by
first actual display data read for 8080-series interface.
MPU 4-lines Serial Peripheral Interface
The 4-lines serial peripheral Interface consists of serial clock SCK, serial data SDA,
shifted into 8-bit shift register on every rising edge of SCK in the order of data bit 7, data bit 6 …… data bit 0.
Display Data RAM or command register at the same clock. Please refer to Figure 21 & Figure 23 on page 62 &
64 for serial interface timing.
D/
W
C
( WR )
write column address
is sampled on every eighth clock to determine whether the data byte in the shift register is written to the
D/
C
www.DataSheet4U.com
input. The E input serves as data latch signal (clock) when high provided that CS is low. Please
N
P 19/69 Jul 2004
dummy read
CS
data read1
n
is low. Whether writing the display data to the GDDRAM or
15
D/
data read 2
CS
– D
C
n+1
. A dummy read is also required before the
0
,
is low. Whether reading the display data
R
RD
/
W
,
,
WR
D/
D/ , E and CS .
C
C
,
.
D/
data read 3
D/
WR
C
C
n+2
and
and
input serves as data
CS
Solomon Systech
www.DataSheet
www.DataSheet4U
www.DataSheet
www.DataSheet
CS
R
. SDA is
/
.
W
RD
R
input
/
W
input
4U
4U.com
4U
.com
.com
.com