XC3S1000L-4FT256C Xilinx, Inc., XC3S1000L-4FT256C Datasheet
XC3S1000L-4FT256C
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XC3S1000L-4FT256C Summary of contents
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... IMPORTANT NOTE: Each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation in this volume. © 2003–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun- tries. All other trademarks are the property of their respective owners. ...
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R DS099 December 4, 2009 Product Specification ...
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... These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family. © 2003–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun- tries. All other trademarks are the property of their respective owners. ...
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Spartan-3 FPGA Family: Introduction and Ordering Information Architectural Overview The Spartan-3 family architecture consists of five funda- mental programmable functional elements: • Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage elements that can be ...
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R Configuration Spartan-3 FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configura- tion latches (CCLs) that collectively control all functional elements and routing resources. Before powering on the FPGA, configuration data is stored externally in a ...
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Spartan-3 FPGA Family: Introduction and Ordering Information Table 3 shows the number of user I/Os as well as the num- ber of differential I/O pairs available for each device/pack- age combination. Table 3: Spartan-3 Device I/O Chart (1) VQ100 CP132 ...
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R Package Marking Figure 2 shows the top marking for Spartan-3 FPGAs in the quad-flat packages. Figure 3 shows the top marking for Spartan-3 FPGAs in BGA packages except the 132-ball chip-scale package (CP132 and CPG132). The markings for the ...
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Spartan-3 FPGA Family: Introduction and Ordering Information Ordering Information Spartan-3 FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The Pb-free packages include a special ‘G’ character in the ordering code. Standard Packaging Example: Device ...
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R Revision History Date Version No. 04/11/03 1.0 Initial Xilinx release. 04/24/03 1.1 Updated block RAM, DCM, and multiplier counts for the XC3S50. 12/24/03 1.2 Added the FG320 package. 07/13/04 1.3 Added information on Pb-free packaging options. 01/17/05 1.4 Referenced ...
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Spartan-3 FPGA Family: Introduction and Ordering Information 10 10 www.xilinx.com R DS099-1 (v2.5) December 4, 2009 Product Specification ...
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... ISE iMPACT Programming Examples © 2003–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun- tries. All other trademarks are the property of their respective owners. ...
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Spartan-3 FPGA Family: Functional Description IOBs For additional information, refer to the “Using I/O Resources” chapter in UG331. IOB Overview The Input/Output Block (IOB) provides a programmable, bidirectional interface between an I/O pin and the FPGA’s internal logic. A simplified ...
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TCE OTCLK1 CK SR OCE OTCLK2 IQ1 D CE ICLK1 CK SR ICE IQ2 D CE ICLK2 CK SR ...
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Spartan-3 FPGA Family: Functional Description According to Figure 5, the clock line OTCLK1 connects the CK inputs of the upper registers on the output and three-state paths. Similarly, OTCLK2 connects the CK inputs for the lower registers on the output ...
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R DCM 180˚ 0˚ CLK1 DDR MUX D2 Q2 CLK2 Figure 6: Clocking the DDR Register Pull-Up and Pull-Down Resistors The optional pull-up and pull-down resistors are intended to establish High and Low levels, respectively, at unused I/Os. ...
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Spartan-3 FPGA Family: Functional Description control IOSTANDARD, refer to the “Using I/O Resources” chapter in UG331. Together with placing the appropriate I/O symbol, two exter- nally applied voltage levels, V CCO desired signal standard. The V CCO the output driver. ...
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R DCI answers these concerns by providing two kinds of on-chip terminations: Parallel terminations make use of an integrated resistor network. Series terminations result from controlling the impedance of output drivers. DCI actively adjusts both parallel and series terminations to ...
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Spartan-3 FPGA Family: Functional Description Table 9: DCI I/O Standards (Continued) Category of Signal Signal Standard Standard (IOSTANDARD) Stub Series SSTL18_I_DCI Terminated Logic SSTL2_I_DCI SSTL2_II_DCI DIFF_SSTL2_II_DCI Differential Low-Voltage LVDS_25_DCI Differential LVDSEXT_25_DCI Signaling Notes: 1. DCI signal standards are not supported ...
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R Table 10: DCI Terminations Termination Controlled impedance output driver Controlled output driver with half impedance Single resistor Split resistors Split resistors with output driver impedance fixed to 25Ω Notes: 1. The value equivalent to the characteristic ...
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Spartan-3 FPGA Family: Functional Description The DCI feature operates independently for each of the device’s eight banks. Each bank has an ‘N’ reference pin (VRN) and a ‘P’ reference pin, (VRP), to calibrate driver and termination resistance. Only when using ...
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R 2. Set all V lines associated with the (interconnected) CCO bank to the same voltage level. 3. The V levels used by all standards assigned to the CCO I/Os of the (interconnected) bank(s) must agree. The Xilinx development software ...
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Spartan-3 FPGA Family: Functional Description . Switch Matrix SHIFTOUT SHIFTIN CLB Overview For more details on the CLBs, refer to the “Using Config- urable Logic Blocks” chapter in UG331. The Configurable Logic Blocks (CLBs) constitute the main logic resource for ...
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R Notes: 1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. The index i can depending on the slice. In this position, the ...
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Spartan-3 FPGA Family: Functional Description The carry chain, together with various dedicated arithmetic logic gates, support fast and efficient implementations of math operations. The carry chain enters the slice as CIN and exits as COUT. Five multiplexers control the chain: ...
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R Block RAM Overview All Spartan-3 devices support block RAM, which is orga- nized as configurable, synchronous 18Kbit blocks. Block RAM stores relatively large amounts of data more efficiently than the distributed RAM feature described earlier. (The lat- ter is ...
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Spartan-3 FPGA Family: Functional Description RAMB16_Sw WEA ENA SSRA CLKA ADDRA[r –1:0] A DIA[w –1:0] A DIPA[3:0] WEB ENB SSRB CLKB ADDRB[r –1:0] B DIB[w –1:0] B DIPB[3:0] (a) Dual-Port Notes and w are integers representing the total ...
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R Table 12: Block RAM Port Signals (Continued) Port A Port B Signal Signal Signal Description Name Data Output DOA Bus Parity Data DOPA Output(s) Write Enable WEA Clock Enable ENA Set/Reset SSRA Clock CLKA DS099-2 (v2.5) December 4, 2009 ...
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Spartan-3 FPGA Family: Functional Description Port Aspect Ratios On a given port possible to select a number of different possible widths (w – p) for the DI/DO buses as shown in Table 13. These two buses always have ...
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R CLK WE DI ADDR DO 0000 EN DISABLED Figure 13: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that location is ...
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Spartan-3 FPGA Family: Functional Description CLK WE DI ADDR DO 0000 EN DISABLED Figure 15: Waveforms of Block RAM Data Operations with NO_CHANGE Selected Dedicated Multipliers All Spartan-3 devices provide embedded multipliers that accept two 18-bit words as inputs to ...
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R Table 14: Embedded Multiplier Primitives Descriptions Signal Name Direction A[17:0] Input Apply one 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before the enabled rising edge of CLK. B[17:0] Input Apply the other 18-bit multiplicand ...
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Spartan-3 FPGA Family: Functional Description PSINCDEC PSEN PSCLK CLKIN CLKFB RST Figure 17: DCM Functional Blocks and Associated Signals The DCM has four functional Delay-Locked Loop (DLL), the Digital Frequency Synthe- sizer (DFS), the Phase Shifter (PS), and the Status ...
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R The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as described in Table 15. The clock outputs drive simulta- neously; however, the High Frequency ...
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Spartan-3 FPGA Family: Functional Description Table 16: DLL Attributes Attribute CLK_FEEDBACK DLL_FREQUENCY_MODE CLKIN_DIVIDE_BY_2 CLKDV_DIVIDE DUTY_CYCLE_CORRECTION DLL Clock Input Connections An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG), which directly accesses the glo- bal clock ...
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R FPGA CLK90 BUFG CLK180 CLKIN CLK270 CLKDV DCM CLK2X CLK2X180 CLKFB CLK0 CLK0 (a) On-Chip with CLK0 Feedback FPGA CLK90 IBUFG CLK180 CLKIN CLK270 CLKDV DCM CLK2X CLK2X180 CLKFB CLK0 IBUFG CLK0 (c) Off-Chip with CLK0 Feedback Notes: 1. ...
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Spartan-3 FPGA Family: Functional Description Their relative timing in the Low Frequency Mode is shown in Figure 20. The CLK90, CLK180 and CLK270 outputs are not available when operating in the High Frequency mode. (See the description of the DLL_FREQUENCY_MODE ...
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R Digital Frequency Synthesizer (DFS) The DFS component generates clock signals the frequency of which is a product of the clock frequency at the CLKIN input and a ratio of two user-determined integers. Because of the wide range of possible ...
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Spartan-3 FPGA Family: Functional Description DFS Clock Output Connections There are two basic cases that determine how to connect the DFS clock outputs: on-chip and off-chip, which are illus- trated in Figure 19a and Figure 19c, respectively. This is similar ...
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R a. CLKOUT_PHASE_SHIFT = NONE b. CLKOUT_PHASE_SHIFT = FIXED Shift Range over all P Values: c. CLKOUT_PHASE_SHIFT = VARIABLE Shift Range over all P Values: Shift Range over all N Values: Notes represents the integer value ranging from ...
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Spartan-3 FPGA Family: Functional Description Table 20: Signals for Variable Phase Mode Signal Direction (1) PSEN Input Enables PSCLK for variable phase adjustment. (1) PSCLK Input Clock to synchronize phase shift adjustment. (1) PSINCDEC Input Chooses between increment and decrement ...
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R Table 22: DCM STATUS Bus Bit Name 0 Phase Shift A value of 1 indicates a phase shift overflow when one of two conditions occurs: Overflow • • 1 CLKIN Input A value of 1 indicates that the CLKIN ...
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Spartan-3 FPGA Family: Functional Description Table 24: BUFGMUX Select Mechanism S Input 0 1 The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a short setup ...
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R 4 DCM 4 DCM DS099-2 (v2.5) December 4, 2009 Product Specification GCLK6 GCLK4 GCLK5 GCLK7 4 4 BUFGMUX 4 • • • Horizontal Spine • • • BUFGMUX 4 GCLK3 GCLK1 GCLK2 GCLK0 Figure 22: ...
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Spartan-3 FPGA Family: Functional Description Interconnect Interconnect (or routing) passes signals among the various functional elements of Spartan-3 devices. There are four kinds of interconnect: Long lines, Hex lines, Double lines, and Direct lines. Long lines connect to one out ...
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R Configuration Spartan-3 devices are configured by loading application specific configuration data into the internal configuration memory. Configuration is carried out using a subset of the device pins, some of which are "Dedicated" to one function only, while others, indicated ...
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Spartan-3 FPGA Family: Functional Description 5 (VCCO_5). All the signals used in the serial configuration modes rely on VCCO_4 power. Signals used in the parallel configuration modes and Readback require from VCCO_5 as well as from VCCO_4. Both the Dedicated ...
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R 3.3V: XCF0xS 1.8V: XCFxxP V CCO V CCINT Platform Flash PROM XCF0xS or XCFxxP OE/RESET GND Notes: 1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for ...
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Spartan-3 FPGA Family: Functional Description when operating in the User mode. This is accomplished by setting the Persist option to Yes. Multiple FPGAs can be configured using the Slave Parallel mode and can be made to start-up simultaneously. Figure 25 ...
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R Notes: 1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last FPGA to be configured in the chain shown above (or for the single FPGA ...
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Spartan-3 FPGA Family: Functional Description Figure 27: Configuration Flow Diagram for the Serial and Parallel Modes 50 54 Set PROG_B Low Power-On after Power-On V >1V CCINT No and V > 2V CCAUX and V Bank 4 > 1V CCO ...
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R and V No (JTAG port becomes No Figure 28: Boundary-Scan Configuration Flow Diagram DS099-2 (v2.5) December 4, 2009 Product Specification Set PROG_B Low Power-On after Power-On V >1V CCINT and V > CCAUX Bank 4 > 1V ...
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... Xilinx FPGAs, including some with integrated multi-rail regulators specifically designed for Spartan-3 FPGAs. The vendor solution guides as well as Xilinx power estimation and analysis tools. Power Distribution System (PDS) Design and Bypass/Decoupling Capacitors Good power distribution system (PDS) design is important ...
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R threshold levels (see Table 28, page plies reach their respective threshold, the POR reset is released and the FPGA begins its configuration process. Because the three supply inputs must be valid to release the POR reset and can be ...
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Spartan-3 FPGA Family: Functional Description Revision History Date Version No. 04/11/03 1.0 Initial Xilinx release 05/19/03 1.1 Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions. 07/11/03 1.2 Explained the configuration port Persist option in Figure 6 the same ...
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... GND © 2003–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun- tries. All other trademarks are the property of their respective owners. DS099-3 (v2.5) December 4, 2009 ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 27: Absolute Maximum Ratings (Continued) Symbol Description Input clamp current per I/O pin Electrostatic Discharge Voltage pins relative ESD to GND T Junction temperature J T Soldering temperature SOL ...
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R Table 29: Power Voltage Ramp Time Requirements Symbol Description T V ramp time for all eight banks CCO CCO T V ramp time, only if V CCINT CCINT in three-rail power-on sequence Notes limit exists, this ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 31: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX ΔV (2) Voltage variance on ...
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R Table 32: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (Continued) Symbol Description (3) R Equivalent resistance of pull-down resistor PD at User I/O, Dual-Purpose, and Dedicated pins, driven from I RPD R Value of external reference ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 33: Quiescent Supply Current Characteristics Symbol Description I Quiescent V CCINTQ CCINT I Quiescent V supply current CCOQ CCO I Quiescent V CCAUXQ CCAUX Notes: 1. The numbers in this table are ...
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R Table 34: Recommended Operating Conditions for User I/Os Using Single-Ended Standards Signal Standard (IOSTANDARD) Min (V) Nom (V) (3) GTL - GTL_DCI - (3) GTLP - GTLP_DCI - HSLVDCI_15 1.4 HSLVDCI_18 1.7 HSLVDCI_25 2.3 HSLVDCI_33 3.0 HSTL_I, HSTL_I_DCI 1.4 ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 35: DC Characteristics of User I/Os Using Single-Ended Standards Signal Standard (IOSTANDARD) and Current Drive Attribute (mA) GTL GTL_DCI GTLP GTLP_DCI HSLVDCI_15 HSLVDCI_18 HSLVDCI_25 HSLVDCI_33 HSTL_I HSTL_I_DCI HSTL_III HSTL_III_DCI HSTL_I_18 HSTL_I_DCI_18 HSTL_II_18 ...
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R Table 35: DC Characteristics of User I/Os Using Single-Ended Standards (Continued) Signal Standard (IOSTANDARD) and Current Drive Attribute (mA) (4) LVCMOS33 LVDCI_33, LVDCI_DV2_33 (4) LVTTL ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Internal Logic V V GND level Table 36: Recommended Operating Conditions for User I/Os Using Differential Signal Standards Signal Standard (IOSTANDARD) Min (V) LDT_25 (ULVDS_25) 2.375 LVDS_25, LVDS_25_DCI 2.375 BLVDS_25 2.375 LVDSEXT_25, 2.375 ...
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R Internal Logic V OUTN V OUTP GND level Table 37: DC Characteristics of User I/Os Using Differential Signal Standards (1) Mask Signal Standard Revision LDT_25 (ULVDS_25) All LVDS_25 All ‘E’ (6) BLVDS_25 All LVDSEXT_25 All ‘E’ (6) LVPECL_25 All ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Switching Characteristics All Spartan-3 devices are available in two speed grades: –4 and the higher performance –5. Switching characteristics in this document may be designated as Advance, Preliminary, or Production. Each category is ...
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R I/O Timing Table 39: Pin-to-Pin Clock-to-Output Times for the IOB Output Path Symbol Description Clock-to-Output Times T When reading from the Output ICKOFDCM Flip-Flop (OFF), the time from the active transition on the Global Clock pin to data appearing ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 40: System-Synchronous Pin-to-Pin Setup and Hold Times for the IOB Input Path Symbol Description Setup Times T When writing to the Input PSDCM Flip-Flop (IFF), the time from the setup of data ...
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R Table 41: Setup and Hold Times for the IOB Input Path Symbol Description Setup Times T Time from the setup of data at the Input IOPICK pin to the active transition at the ICLK input of the Input Flip-Flop ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 42: Propagation Times for the IOB Input Path Symbol Description Propagation Times T The time it takes for data to IOPLI travel from the Input pin through the IFF latch to the ...
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R Table 43: Input Timing Adjustments for IOB Add the Adjustment Below Convert Input Time from LVCMOS25 to the Speed Grade Following Signal Standard (IOSTANDARD) -5 Single-Ended Standards GTL, GTL_DCI 0.44 GTLP, GTLP_DCI 0.36 HSLVDCI_15 0.51 HSLVDCI_18 0.29 HSLVDCI_25 0.51 ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 44: Timing for the IOB Output Path Symbol Description Clock-to-Output Times T When reading from the Output IOCKP Flip-Flop (OFF), the time from the active transition at the OTCLK input to data ...
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R Table 45: Timing for the IOB Three-State Path Symbol Description Synchronous Output Enable/Disable Times T Time from the active transition at the IOCKHZ OTCLK input of the Three-state Flip-Flop (TFF) to when the Output pin enters the high-impedance state ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 46: Output Timing Adjustments for IOB Add the Adjust- Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards GTL GTL_DCI GTLP ...
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R Table 46: Output Timing Adjustments for IOB (Continued) Add the Adjust- Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS33 Slow ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test condi- tions. Table 47 presents the conditions to use for each stan- dard. The method ...
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R Table 47: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) V REF LVCMOS18 - LVDCI_18 LVDCI_DV2_18 HSLVDCI_18 LVCMOS25 - LVDCI_25 LVDCI_DV2_25 HSLVDCI_25 LVCMOS33 - LVDCI_33 LVDCI_DV2_33 HSLVDCI_33 LVTTL - PCI33_3 Rising - Falling SSTL18_I 0.9 SSTL18_I_DCI ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 47: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) V REF DIFF_SSTL2_II - DIFF_SSTL2_II_DCI Notes: 1. Descriptions of the relevant symbols are as follows: – V The reference voltage ...
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R Simultaneously Switching Output Guidelines This section provides guidelines for the maximum allowable number of Simultaneous Switching Outputs (SSOs). These guidelines describe the maximum number of user I/O pins given output signal standard, that should simulta- neously switch ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 49: Recommended Number of Simultaneously Switching Outputs per V -GND Pair CCO Signal Standard VQ TQ (IOSTANDARD) 100 144 Single-Ended Standards GTL 0 0 GTL_DCI 0 0 GTLP 0 0 GTLP_DCI 0 ...
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R Table 49: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (Continued) CCO Signal Standard VQ TQ (IOSTANDARD) 100 144 LVCMOS33 Slow ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Internal Logic Timing Table 50: CLB Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, CKO the time from the active transition at the CLK input to data appearing at ...
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R Table 51: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data SHCKO appearing on the distributed RAM output Setup Times T Setup time of data at the BX ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 53: Synchronous Multiplier Timing Symbol Description Clock-to-Output Times T When reading from the MULTCK Multiplier, the time from the active transition at the C clock input to data appearing ...
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R Table 55: Block RAM Timing Symbol Description Clock-to-Output Times T When reading from the Block BCKO RAM, the time from the active transition at the CLK input to data appearing at the DOUT output Setup Times T Time from ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Fre- quency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL ...
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R Table 58: Switching Characteristics for the DLL Symbol Output Frequency Ranges CLKOUT_FREQ_1X_LF Frequency for the CLK0, CLK90, CLK180, and CLK270 outputs CLKOUT_FREQ_1X_HF Frequency for the CLK0 and CLK180 outputs (3) CLKOUT_FREQ_2X_LF Frequency for the CLK2X and CLK2X180 outputs CLKOUT_FREQ_DV_LF ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Table 58: Switching Characteristics for the DLL (Continued) Symbol Lock Time LOCK_DLL When using the DLL alone: The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED ...
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R Table 60: Switching Characteristics for the DFS Symbol Output Frequency Ranges CLKOUT_FREQ_FX_LF Frequency for the CLKFX and CLKFX180 outputs CLKOUT_FREQ_FX_HF Output Clock Jitter CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180 outputs (4) Duty Cycle CLKOUT_DUTY_CYCLE_FX Duty cycle precision ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Phase Shifter (PS) Phase shifter operation is only supported if the DLL is in low-frequency mode, see software version 10.1.03 (or later). Table 61: Recommended Operating Conditions for the PS in Variable Phase ...
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R Miscellaneous DCM Timing Table 63: Miscellaneous DCM Timing Symbol DCM_INPUT_CLOCK_STOP Maximum duration that the CLKIN and CLKFB signals can be stopped DCM_RST_PW_MIN Minimum duration of a RST pulse width (3) DCM_RST_PW_MAX Maximum duration of a RST pulse width (4) ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Configuration and JTAG Timing V CCINT (Supply) V CCAUX (Supply) V Bank 4 CCO (Supply) PROG_B (Input) INIT_B (Open-Drain) CCLK (Output) Notes: 1. The and V CCINT CCAUX 2. ...
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R PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) DOUT (Output) Figure 35: Waveforms for Master and Slave Serial Configuration Table 65: Timing for the Master and Slave Serial Configuration Modes Symbol Clock-to-Output Times T The time from the falling ...
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Spartan-3 FPGA Family: DC and Switching Characteristics PROG_B (Input) INIT_B (Open-Drain) CS_B (Input) RDWR_B (Input) CCLK (Input/Output (Inputs) High-Z BUSY (Output) Notes: 1. Switching RDWR_B High or Low while holding CS_B Low asynchronously aborts configuration. Figure 36: ...
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R Table 66: Timing for the Master and Slave Parallel Configuration Modes (Continued) Symbol Hold Times T The time from the rising transition at the CCLK pin to the point SMCCD when data is last held at the D0-D7 pins ...
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Spartan-3 FPGA Family: DC and Switching Characteristics TCK (Input) TMS (Input) TDI (Input) TDO (Output) Table 67: Timing for the JTAG Test Access Port Symbol Clock-to-Output Times T The time from the falling transition on the TCK pin to data ...
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R Revision History Date Version No. 04/11/03 1.0 Initial Xilinx release. 07/11/03 1.1 Extended Absolute Maximum Rating for junction temperature in quiescent supply current 02/06/04 1.2 Revised V number current numbers LVDCI_DV2 and LVPECL standards Table 66). 03/04/04 1.3 Added ...
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Spartan-3 FPGA Family: DC and Switching Characteristics Date Version No. 04/26/06 2.1 Updated document links. 05/25/07 2.2 Improved absolute maximum voltage specifications in allowance. Improved XC3S50 HBM ESD to 2000V in data, improved (reduced) the maximum quiescent current limits for ...
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... There are two DCI pins per I/O bank. © 2003–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun- tries. All other trademarks are the property of their respective owners. ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 68: Types of Pins on Spartan-3 FPGAs (Continued) Type/ Color Code VREF Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins in the same bank, provides a reference ...
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R Table 69: Spartan-3 FPGA Pin Definitions Pin Name Direction I/O: General-purpose I/O pins I/O User-defined as input, output, bidirectional, three-state output, open-drain output, open-source output I/O_Lxxy_# User-defined as input, output, bidirectional, three-state output, open-drain output, open-source output DUAL: Dual-purpose ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 69: Spartan-3 FPGA Pin Definitions (Continued) Pin Name Direction IO_Lxxy_#/INIT_B Bidirectional (open-drain) during configuration User I/O after configuration DCI: Digitally Controlled Impedance reference resistor input pins IO_Lxxy_#/VRN_# or Input when using DCI IO/VRN_# Otherwise, ...
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R Table 69: Spartan-3 FPGA Pin Definitions (Continued) Pin Name Direction DONE Bidirectional with open-drain or totem-pole Output M0, M1, M2 Input HSWAP_EN Input JTAG: JTAG interface pins (pull-up resistor to VCCAUX always active during configuration, regardless of HSWAP_EN pin) ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 69: Spartan-3 FPGA Pin Definitions (Continued) Pin Name Direction VCCAUX: Auxiliary voltage supply pins VCCAUX Supply VCCINT: Internal core voltage supply pins VCCINT Supply GND: Ground supply pins GND Supply N.C.: Unconnected package pins ...
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R Bank 0 Bank 1 Bank 5 Bank 4 DUAL Type: Dual-Purpose Configuration and I/O Pins These pins serve dual purposes. The user-I/O pins are tem- porarily borrowed during the configuration process to load configuration data into the FPGA. After ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 70: Dual-Purpose Pins Used in Master or Slave Serial Mode Pin Name Direction DIN Input Serial Data Input: During the Master or Slave Serial configuration modes, DIN is the serial configuration data input, and ...
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R Assert Low both the chip-select pin, CS_B, and the read/write control pin, RDWR_B, to write the configuration data byte presented on the D0-D7 pins to the FPGA on a rising-edge of the configuration clock, CCLK. The order of CS_B ...
Page 108
Spartan-3 FPGA Family: Pinout Descriptions Table 71: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes (Continued) Pin Name Direction RDWR_B Input Read/Write Control for Parallel Mode Configuration: In Master and Slave Parallel modes, assert this pin Low together with CS_B ...
Page 109
R One of eight I/O Banks User I/O User I/O (a) No termination DCI: User I/O or Digitally Controlled Impedance Resistor Reference Input These pins are individual user-I/O pins unless one of the I/O standards used in the bank requires ...
Page 110
Spartan-3 FPGA Family: Pinout Descriptions CCLK: Configuration Clock The configuration clock signal on this pin synchronizes the reading or writing of configuration data. The CCLK pin is an input-only pin for the Slave Serial and Slave Parallel config- uration modes. ...
Page 111
R Table 73: DonePin and DriveDone Bitstream Option Interaction Single- or Multi- DonePin DriveDone FPGA Design Pullnone No Single Pullnone No Pullnone Yes Single Pullnone Yes Pullup No Single Pullup No Pullup Yes Single Pullup Yes M2, M1, M0: Configuration ...
Page 112
Spartan-3 FPGA Family: Pinout Descriptions . Table 76: JTAG Pin Descriptions Pin Name Direction TCK Input Test Clock: The TCK clock signal synchronizes all boundary scan operations on its rising edge. TDI Input Test Data Input: TDI is the serial ...
Page 113
R The TDO output can directly drive a 3.3V input but with reduced noise immunity. See 3.3V-Tolerant Configuration Interface, page 46 or XAPP453: The 3.3V Configuration of for additional details. Spartan-3 FPGAs The following interface precautions are recommended when connecting ...
Page 114
Spartan-3 FPGA Family: Pinout Descriptions VCCAUX Type: Voltage Supply for Auxiliary Logic The VCCAUX pins supply power to various auxiliary cir- cuits, such as to the Digital Clock Managers (DCMs), the JTAG pins, and to the dedicated configuration pins (CON- ...
Page 115
R Table 78: Pin Behavior After Power-Up, During Configuration (Continued) Serial Modes Master Pin Name <0:0:0> IO_Lxxy_#/ D5 IO_Lxxy_#/ D6 IO_Lxxy_#/ D7 IO_Lxxy_#/ CS_B IO_Lxxy_#/ RDWR_B IO_Lxxy_#/ DOUT (O) BUSY/DOUT DUAL: Dual-purpose configuration pins (INIT_B has a pull-up resistor to ...
Page 116
Spartan-3 FPGA Family: Pinout Descriptions Table 78: Pin Behavior After Power-Up, During Configuration (Continued) Serial Modes Master Pin Name <0:0:0> M1 M1=0 (I) M0 M0=0 (I) HSWAP_EN HSWAP_EN (I) JTAG: JTAG interface pins (pull-up resistor to VCCAUX always active during ...
Page 117
R Bitstream Options Table 79 lists the various bitstream options that affect pins on a Spartan-3 FPGA. The table shows the names of the affected pins, describes the function of the bitstream option, Table 79: Bitstream Options Affecting Spartan-3 Pins ...
Page 118
Spartan-3 FPGA Family: Pinout Descriptions Table 79: Bitstream Options Affecting Spartan-3 Pins (Continued) Affected Pin Name(s) M0 After configuration, this bitstream option either pulls M0 to VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows M0 ...
Page 119
R Package Overview Table 80 shows the 10 low-cost, space-saving production package styles for the Spartan-3 family. Each package style is available as a standard and an environmentally-friendly lead-free (Pb-free) option. The Pb-free packages include an extra ‘G’ in the ...
Page 120
Spartan-3 FPGA Family: Pinout Descriptions Mechanical Drawings Detailed mechanical drawings for each package type are available from the Xilinx website at the specified location in Table 82. Table 82: Xilinx Package Mechanical Drawings Package VQ100 and VQG100 (1) CP132 and ...
Page 121
R Table 84: Maximum User I/Os by Package Maximum Device Package User I/Os XC3S50 VQ100 XC3S200 VQ100 (1) XC3S50 CP132 XC3S50 TQ144 XC3S200 TQ144 XC3S400 TQ144 XC3S50 PQ208 XC3S200 PQ208 XC3S400 PQ208 XC3S200 FT256 XC3S400 FT256 XC3S1000 FT256 XC3S400 FG320 ...
Page 122
Spartan-3 FPGA Family: Pinout Descriptions Package Thermal Characteristics The power dissipated by an FPGA application has implica- tions on package selection and system design. The power consumed by a Spartan-3 FPGA is reported using either the XPower Estimator (XPE) or ...
Page 123
R Table 85: Spartan-3 Package Thermal Characteristics Junction-to- Package Device Case (θ VQ(G)100 XC3S50 XC3S200 (1) CP(G)132 XC3S50 TQ(G)144 XC3S50 XC3S200 XC3S400 PQ(G)208 XC3S50 XC3S200 XC3S400 FT(G)256 XC3S200 XC3S400 XC3S1000 FG(G)320 XC3S400 XC3S1000 XC3S1500 FG(G)456 XC3S400 XC3S1000 XC3S1500 XC3S2000 FG(G)676 ...
Page 124
Spartan-3 FPGA Family: Pinout Descriptions VQ100: 100-lead Very-thin Quad Flat Package The XC3S50 and the XC3S200 devices are available in the 100-lead very-thin quad flat package, VQ100. Both devices share a common footprint for this package as shown in Table ...
Page 125
R Table 86: VQ100 Package Pinout XC3S50 XC3S200 Bank Pin Name 7 IO_L23P_7 7 IO_L40N_7/VREF_7 7 IO_L40P_7 7 VCCO_7 N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A ...
Page 126
Spartan-3 FPGA Family: Pinout Descriptions VQ100 Footprint IO_L01P_7/VRN_7 1 2 IO_L01N_7/VRP_7 GND 3 IO_L21P_7 4 IO_L21N_7 5 6 VCCO_7 7 VCCAUX IO_L23P_7 8 IO_L23N_7 9 10 GND IO_L40P_7 11 IO_L40N_7/VREF_7 12 IO_L40P_6/VREF_6 13 IO_L40N_6 14 IO_L24P_6 15 IO_L24N_6/VREF_6 16 17 ...
Page 127
R CP132: 132-Ball Chip-Scale Package Note: The CP132 and CPG132 packages are being discontinued and are not recommended for new designs. See inx.com/support/documentation/spartan-3.htm#19600 for the latest updates. The XC3S50 is available in the 132-ball chip-scale package, CP132. The pinout and ...
Page 128
Spartan-3 FPGA Family: Pinout Descriptions Table 88: CP132 Package Pinout Bank XC3S50 Pin Name 6 IO_L20N_6 6 IO_L20P_6 6 IO_L22N_6 6 IO_L22P_6 6 IO_L23N_6 6 IO_L23P_6 6 IO_L24N_6/VREF_6 6 IO_L24P_6 6 IO_L40N_6 6 IO_L40P_6/VREF_6 7 IO_L01N_7/VRP_7 7 IO_L01P_7/VRN_7 7 IO_L21N_7 ...
Page 129
R User I/Os by Bank Table 89 indicates how the 89 available user-I/O pins are distributed between the eight I/O banks on the CP132 pack- Table 89: User I/Os Per Bank for XC3S50 in CP132 Package Package Edge I/O Bank ...
Page 130
Spartan-3 FPGA Family: Pinout Descriptions CP132 Footprint I/O VCCO_ A PROG_B TDI L01N_0 VRP_0 I/O I/O HSWAP_ B L01P_7 L01N_7 EN VRN_7 VRP_7 VCCO_ I/O C GND L01P_0 LEFT L21N_7 VRN_0 I/O I/O I/O D L22N_7 L22P_7 ...
Page 131
R TQ144: 144-lead Thin Quad Flat Package The XC3S50, the XC3S200, and the XC3S400 are avail- able in the 144-lead thin quad flat package, TQ144. All devices share a common footprint for this package as shown in Table 90 and ...
Page 132
Spartan-3 FPGA Family: Pinout Descriptions Table 90: TQ144 Package Pinout (Continued) XC3S50 XC3S200 XC3S400 Bank Pin Name 5 IO_L01N_5/RDWR_B 5 IO_L01P_5/CS_B 5 IO_L28N_5/D6 5 IO_L28P_5/D7 5 IO_L31N_5/D4 5 IO_L31P_5/D5 5 IO_L32N_5/GCLK3 5 IO_L32P_5/GCLK2 6 IO_L01N_6/VRP_6 6 IO_L01P_6/VRN_6 6 IO_L20N_6 6 ...
Page 133
R User I/Os by Bank Table 91 indicates how the available user-I/O pins are dis- tributed between the eight I/O banks on the TQ144 pack- age. Table 91: User I/Os Per Bank in TQ144 Package Package Edge I/O Bank 0 ...
Page 134
Spartan-3 FPGA Family: Pinout Descriptions TQ144 Footprint IO_L01P_7/VRN_7 1 IO_L01N_7/VRP_7 2 X VCCO_LEFT 3 IO/VREF_7 4 IO_L20P_7 5 IO_L20N_7 6 IO_L21P_7 7 IO_L21N_7 8 GND 9 IO_L22P_7 10 IO_L22N_7 11 IO_L23P_7 12 IO_L23N_7 13 IO_L24P_7 14 IO_L24N_7 15 GND 16 ...
Page 135
R PQ208: 208-lead Plastic Quad Flat Pack The 208-lead plastic quad flat package, PQ208, supports three different Spartan-3 devices, including the XC3S50, the XC3S200, and the XC3S400. The footprints for the XC3S200 and XC3S400 are identical, as shown in and ...
Page 136
Spartan-3 FPGA Family: Pinout Descriptions Table 92: PQ208 Package Pinout (Continued) XC3S200 XC3S50 XC3S400 Bank Pin Name Pin Name 2 IO_L22P_2 IO_L22P_2 2 IO_L23N_2/ IO_L23N_2/ VREF_2 VREF_2 2 IO_L23P_2 IO_L23P_2 2 IO_L24N_2 IO_L24N_2 2 IO_L24P_2 IO_L24P_2 2 N. ...
Page 137
R Table 92: PQ208 Package Pinout (Continued) XC3S200 XC3S50 XC3S400 Bank Pin Name Pin Name 5 IO_L31P_5/ IO_L31P_5 IO_L32N_5/ IO_L32N_5/ GCLK3 GCLK3 5 IO_L32P_5/ IO_L32P_5/ GCLK2 GCLK2 5 VCCO_5 VCCO_5 5 VCCO_5 VCCO_5 6 N. ...
Page 138
Spartan-3 FPGA Family: Pinout Descriptions Table 92: PQ208 Package Pinout (Continued) XC3S200 XC3S50 XC3S400 Bank Pin Name Pin Name N/A GND GND N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX ...
Page 139
R Table 94: User I/Os Per Bank for XC3S200 and XC3S400 in PQ208 Package Package Edge I/O Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 DS099-4 (v2.5) December 4, 2009 Product Specification All Possible I/O ...
Page 140
Spartan-3 FPGA Family: Pinout Descriptions PQ208 Footprint Left Half of Package (top view) XC3S50 (124 max. user I/O) I/O: Unrestricted, 72 general-purpose user I/O VREF: User I/O or input 16 voltage reference for bank N.C.: Unconnected pins for 17 XC3S50 ...
Page 141
R Bank 1 Bank 4 DS099-4 (v2.5) December 4, 2009 Product Specification Spartan-3 FPGA Family: Pinout Descriptions IO_L01N_2/VRP_2 156 IO_L01P_2/VRN_2 155 IO/VREF_2 ( ) 154 VCCO_2 153 IO_L19N_2 152 GND 151 IO_L19P_2 150 IO_L20N_2 149 IO_L20P_2 148 IO_L21N_2 147 IO_L21P_2 ...
Page 142
Spartan-3 FPGA Family: Pinout Descriptions FT256: 256-lead Fine-pitch Thin Ball Grid Array The 256-lead fine-pitch thin ball grid array package, FT256, supports three different Spartan-3 devices, including the XC3S200, the XC3S400, and the XC3S1000. The footprints for all three devices ...
Page 143
R Table 95: FT256 Package Pinout (Continued) XC3S200 XC3S400 XC3S1000 Bank Pin Name 2 IO_L39N_2 2 IO_L39P_2 2 IO_L40N_2 2 IO_L40P_2/VREF_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 IO_L01N_3/VRP_3 3 IO_L01P_3/VRN_3 3 IO_L16N_3 3 IO_L16P_3 3 IO_L17N_3 3 ...
Page 144
Spartan-3 FPGA Family: Pinout Descriptions Table 95: FT256 Package Pinout (Continued) XC3S200 XC3S400 XC3S1000 Bank Pin Name 5 VCCO_5 IO_L01N_6/VRP_6 6 IO_L01P_6/VRN_6 6 IO_L16N_6 6 IO_L16P_6 6 IO_L17N_6 6 IO_L17P_6/VREF_6 6 IO_L19N_6 6 IO_L19P_6 6 IO_L20N_6 6 ...
Page 145
R Table 95: FT256 Package Pinout (Continued) XC3S200 XC3S400 XC3S1000 Bank Pin Name N/A GND N/A GND N/A GND N/A GND N/A GND N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A ...
Page 146
Spartan-3 FPGA Family: Pinout Descriptions FT256 Footprint I TDI GND L01P_0 VREF_0 VRN_0 I/O I/O B PROG_B L01P_7 GND L01N_0 VRN_7 VRP_0 I/O I/O I/O HSWAP_ C L01N_7 L16P_7 L16N_7 EN VRP_7 VREF_7 I/O ...
Page 147
R FG320: 320-lead Fine-pitch Ball Grid Array The 320-lead fine-pitch ball grid array package, FG320, supports three different Spartan-3 devices, including the XC3S400, the XC3S1000, and the XC3S1500. The footprint for all three devices is identical, as shown in Figure ...
Page 148
Spartan-3 FPGA Family: Pinout Descriptions Table 97: FG320 Package Pinout (Continued) XC3S400 XC3S1000 XC3S1500 Bank Pin Name 2 IO_L19N_2 2 IO_L19P_2 2 IO_L20N_2 2 IO_L20P_2 2 IO_L21N_2 2 IO_L21P_2 2 IO_L22N_2 2 IO_L22P_2 2 IO_L23N_2/VREF_2 2 IO_L23P_2 2 IO_L24N_2 2 ...
Page 149
R Table 97: FG320 Package Pinout (Continued) XC3S400 XC3S1000 XC3S1500 Bank Pin Name 4 VCCO_4 4 VCCO_4 4 VCCO_4 IO/VREF_5 5 IO_L01N_5/RDWR_B 5 IO_L01P_5/CS_B 5 IO_L06N_5 5 IO_L06P_5 5 IO_L10N_5/VRP_5 5 IO_L10P_5/VRN_5 5 ...
Page 150
Spartan-3 FPGA Family: Pinout Descriptions Table 97: FG320 Package Pinout (Continued) XC3S400 XC3S1000 XC3S1500 Bank Pin Name 7 IO_L34N_7 7 IO_L34P_7 7 IO_L35N_7 7 IO_L35P_7 7 IO_L39N_7 7 IO_L39P_7 7 IO_L40N_7/VREF_7 7 IO_L40P_7 7 VCCO_7 7 VCCO_7 7 VCCO_7 N/A ...
Page 151
R User I/Os by Bank Table 98 indicates how the available user-I/O pins are dis- tributed between the eight I/O banks on the FG320 pack- age. Table 98: User I/Os Per Bank in FG320 Package Maximum Package Edge I/O Bank ...
Page 152
Spartan-3 FPGA Family: Pinout Descriptions FG320 Footprint Bank I/O I/O I/O I/O A GND L01N_0 L01P_0 L15N_0 L15P_0 VRP_0 VRN_0 I/O I/O I/O I/O B GND L16P_7 VREF_0 L09N_0 L25N_0 VREF_7 I/O I/O I/O ...
Page 153
R FG456: 456-lead Fine-pitch Ball Grid Array The 456-lead fine-pitch ball grid array package, FG456, supports four different Spartan-3 devices, including the XC3S400, the XC3S1000, the XC3S1500, and the XC3S2000. The footprints for the XC3S1000, the XC3S1500, and the XC3S2000 ...
Page 154
Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 1 IO/VREF_1 IO/VREF_1 1 N. IO/VREF_1 1 IO_L01N_1/ IO_L01N_1/ VRP_1 VRP_1 1 IO_L01P_1/ IO_L01P_1/ VRN_1 VRN_1 1 IO_L06N_1/ ...
Page 155
R Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 2 IO_L40P_2/ IO_L40P_2/ VREF_2 VREF_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 ...
Page 156
Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 4 IO_L24P_4 IO_L24P_4 4 IO_L25N_4 IO_L25N_4 4 IO_L25P_4 IO_L25P_4 4 IO_L27N_4/ IO_L27N_4/ DIN/D0 DIN/D0 4 IO_L27P_4/ IO_L27P_4 ...
Page 157
R Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 6 IO_L19N_6 IO_L19N_6 6 IO_L19P_6 IO_L19P_6 6 IO_L20N_6 IO_L20N_6 6 IO_L20P_6 IO_L20P_6 6 IO_L21N_6 IO_L21N_6 6 IO_L21P_6 IO_L21P_6 6 IO_L22N_6 IO_L22N_6 6 IO_L22P_6 IO_L22P_6 ...
Page 158
Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 7 IO_L40N_7/ IO_L40N_7/ VREF_7 VREF_7 7 IO_L40P_7 IO_L40P_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 ...
Page 159
R User I/Os by Bank Table 100 indicates how the available user-I/O pins are dis- tributed between the eight I/O banks for the XC3S400 in the FG456 package. Similarly, Table 101 Table 100: User I/Os Per Bank for XC3S400 in ...
Page 160
Spartan-3 FPGA Family: Pinout Descriptions FG456 Footprint Left Half of FG456 Package (top view) XC3S400 (264 max. user I/O) I/O: Unrestricted, 196 general-purpose user I/O VREF: User I/O or input 32 voltage reference for bank N.C.: Unconnected pins for 69 ...
Page 161
R Bank I/O I/O I/O I/O L22N_1 I/O VCCAUX L30N_1 L28N_1 L25P_1 I/O I/O I/O I/O I/O I/O L22P_1 L32N_1 L30P_1 L28P_1 L25N_1 L16N_1 GCLK5 I/O I/O I/O I/O L19N_1 L32P_1 GND VCCO_1 ...
Page 162
Spartan-3 FPGA Family: Pinout Descriptions FG676: 676-lead Fine-pitch Ball Grid Array The 676-lead fine-pitch ball grid array package, FG676, supports five different Spartan-3 devices, including the XC3S1000, XC3S1500, XC3S2000, XC3S4000, and XC3S5000. All five have nearly identical footprints but are ...
Page 163
R Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name 0 N. IO_L11N_0 0 N. IO_L11P_0 0 N. IO_L12N_0 0 N. IO_L12P_0 0 IO_L15N_0 IO_L15N_0 0 IO_L15P_0 IO_L15P_0 ...
Page 164
Spartan-3 FPGA Family: Pinout Descriptions Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name IO/VREF_1 IO/VREF_1 1 ...
Page 165
R Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name 1 N. IO_L26P_1 1 IO_L27N_1 IO_L27N_1 1 IO_L27P_1 IO_L27P_1 1 IO_L28N_1 IO_L28N_1 1 IO_L28P_1 IO_L28P_1 1 IO_L29N_1 IO_L29N_1 1 IO_L29P_1 IO_L29P_1 1 IO_L30N_1 IO_L30N_1 ...
Page 166
Spartan-3 FPGA Family: Pinout Descriptions Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name 2 IO_L19N_2 IO_L19N_2 2 IO_L19P_2 IO_L19P_2 2 IO_L20N_2 IO_L20N_2 2 IO_L20P_2 IO_L20P_2 2 IO_L21N_2 IO_L21N_2 2 IO_L21P_2 IO_L21P_2 2 IO_L22N_2 IO_L22N_2 2 ...
Page 167
R Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name 3 IO_L02N_3/VREF_3 IO_L02N_3/VREF_3 3 IO_L02P_3 IO_L02P_3 3 IO_L03N_3 IO_L03N_3 3 IO_L03P_3 IO_L03P_3 3 N. IO_L05N_3 3 N. IO_L05P_3 3 N. ...
Page 168
Spartan-3 FPGA Family: Pinout Descriptions Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name 3 IO_L33N_3 IO_L33N_3 3 IO_L33P_3 IO_L33P_3 3 IO_L34N_3 IO_L34N_3 3 IO_L34P_3/VREF_3 IO_L34P_3/VREF_3 3 IO_L35N_3 IO_L35N_3 3 IO_L35P_3 IO_L35P_3 3 IO_L38N_3 IO_L38N_3 3 ...
Page 169
R Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name 4 IO_L10P_4 IO_L10P_4 4 N. IO_L11N_4 4 N. IO_L11P_4 4 N. IO_L12N_4 4 N. IO_L12P_4 4 IO_L15N_4 IO_L15N_4 ...
Page 170
Spartan-3 FPGA Family: Pinout Descriptions Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name N. ...
Page 171
R Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name 5 N. IO_L26N_5 5 N. IO_L26P_5 5 IO_L27N_5/VREF_5 IO_L27N_5/VREF_5 5 IO_L27P_5 IO_L27P_5 5 IO_L28N_5/D6 IO_L28N_5/D6 5 IO_L28P_5/D7 IO_L28P_5/D7 5 IO_L29N_5 IO_L29N_5 5 ...
Page 172
Spartan-3 FPGA Family: Pinout Descriptions Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name 6 IO_L17P_6/VREF_6 IO_L17P_6/VREF_6 6 IO_L19N_6 IO_L19N_6 6 IO_L19P_6 IO_L19P_6 6 IO_L20N_6 IO_L20N_6 6 IO_L20P_6 IO_L20P_6 6 IO_L21N_6 IO_L21N_6 6 IO_L21P_6 IO_L21P_6 6 ...
Page 173
R Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name 7 IO_L01P_7/VRN_7 IO_L01P_7/VRN_7 7 IO_L02N_7 IO_L02N_7 7 IO_L02P_7 IO_L02P_7 7 IO_L03N_7/VREF_7 IO_L03N_7/VREF_7 7 IO_L03P_7 IO_L03P_7 7 N. IO_L05N_7 7 N. IO_L05P_7 7 ...
Page 174
Spartan-3 FPGA Family: Pinout Descriptions Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name 7 IO_L32P_7 IO_L32P_7 7 IO_L33N_7 IO_L33N_7 7 IO_L33P_7 IO_L33P_7 7 IO_L34N_7 IO_L34N_7 7 IO_L34P_7 IO_L34P_7 7 IO_L35N_7 IO_L35N_7 7 IO_L35P_7 IO_L35P_7 7 ...
Page 175
R Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND ...
Page 176
Spartan-3 FPGA Family: Pinout Descriptions Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A VCCAUX VCCAUX N/A VCCAUX VCCAUX N/A ...
Page 177
R Table 102: FG676 Package Pinout (Continued) XC3S1000 XC3S1500 Bank Pin Name Pin Name VCC M0 M0 AUX VCC M1 M1 AUX VCC M2 M2 AUX VCC PROG_B PROG_B AUX VCC TCK TCK AUX VCC TDI TDI AUX VCC TDO ...
Page 178
Spartan-3 FPGA Family: Pinout Descriptions Table 104: User I/Os Per Bank for XC3S1500 in FG676 Package I/O Maximum Edge Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 Table 105: User I/Os Per Bank for XC3S2000, ...
Page 179
R DS099-4 (v2.5) December 4, 2009 Product Specification Spartan-3 FPGA Family: Pinout Descriptions www.xilinx.com 179 ...
Page 180
Spartan-3 FPGA Family: Pinout Descriptions FG676 Footprint Left Half of Package (top view) XC3S1000 (391 max. user I/O) I/O: Unrestricted, 315 general-purpose user I/O VREF: User I/O or input 40 voltage reference for bank N.C.: Unconnected pins for 98 XC3S1000 ...
Page 181
R Bank I/O I/O I/O I/O L26N_1 L23N_1 VCCAUX I/O L10N_1 L29N_1 L15N_1 VREF_1 I/O I/O I/O I/O I/O I/O L26P_1 L23P_1 L18N_1 L32N_1 L29P_1 L15P_1 L10P_1 GCLK5 I/O I/O I/O I/O I/O ...
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Spartan-3 FPGA Family: Pinout Descriptions FG900: 900-lead Fine-pitch Ball Grid Array The 900-lead fine-pitch ball grid array package, FG900, supports three different Spartan-3 devices, including the XC3S2000, the XC3S4000, and the XC3S5000. The foot- prints for the XC3S4000 and XC3S5000 ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 0 IO_L27N_0 IO_L27N_0 0 IO_L27P_0 IO_L27P_0 0 IO_L28N_0 IO_L28N_0 0 IO_L28P_0 IO_L28P_0 0 IO_L29N_0 IO_L29N_0 0 IO_L29P_0 IO_L29P_0 0 IO_L30N_0 IO_L30N_0 0 IO_L30P_0 IO_L30P_0 0 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 1 IO_L24N_1 IO_L24N_1 1 IO_L24P_1 IO_L24P_1 1 IO_L25N_1 IO_L25N_1 1 IO_L25P_1 IO_L25P_1 1 IO_L26N_1 IO_L26N_1 1 IO_L26P_1 IO_L26P_1 1 IO_L27N_1 IO_L27N_1 ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 2 IO_L28N_2 IO_L28N_2 2 IO_L28P_2 IO_L28P_2 2 IO_L29N_2 IO_L29N_2 2 IO_L29P_2 IO_L29P_2 2 IO_L31N_2 IO_L31N_2 2 IO_L31P_2 IO_L31P_2 2 IO_L32N_2 IO_L32N_2 2 IO_L32P_2 IO_L32P_2 2 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 3 IO_L23N_3 IO_L23N_3 3 IO_L23P_3/ IO_L23P_3/ VREF_3 VREF_3 3 IO_L24N_3 IO_L24N_3 3 IO_L24P_3 IO_L24P_3 3 IO_L26N_3 IO_L26N_3 3 IO_L26P_3 IO_L26P_3 3 ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 4 IO_L15N_4 IO_L15N_4 4 IO_L15P_4 IO_L15P_4 4 IO_L16N_4 IO_L16N_4 4 IO_L16P_4 IO_L16P_4 4 IO_L17N_4 IO_L17N_4 4 IO_L17P_4 IO_L17P_4 4 IO_L18N_4 IO_L18N_4 4 IO_L18P_4 IO_L18P_4 4 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 5 IO_L10N_5/ IO_L10N_5/ VRP_5 VRP_5 5 IO_L10P_5/ IO_L10P_5/ VRN_5 VRN_5 5 IO_L11N_5/ IO_L11N_5/ VREF_5 VREF_5 5 IO_L11P_5 IO_L11P_5 5 IO_L12N_5 IO_L12N_5 ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 6 IO_L07N_6 IO_L07N_6 6 IO_L07P_6 IO_L07P_6 6 IO_L08N_6 IO_L08N_6 6 IO_L08P_6 IO_L08P_6 6 IO_L09N_6/ IO_L09N_6/ VREF_6 VREF_6 6 IO_L09P_6 IO_L09P_6 6 IO_L10N_6 IO_L10N_6 6 IO_L10P_6 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name 7 IO_L04N_7 IO_L04N_7 7 IO_L04P_7 IO_L04P_7 7 IO_L05N_7 IO_L05N_7 7 IO_L05P_7 IO_L05P_7 7 IO_L06N_7 IO_L06N_7 7 IO_L06P_7 IO_L06P_7 7 IO_L07N_7 IO_L07N_7 ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND ...
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R Table 106: FG900 Package Pinout (Continued) XC3S4000 XC3S2000 XC3S5000 Bank Pin Name Pin Name VCCAUX PROG_B PROG_B VCCAUX TCK TCK VCCAUX TDI TDI VCCAUX TDO TDO VCCAUX TMS TMS Table 107: User I/Os Per Bank for XC3S2000 in FG900 ...
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Spartan-3 FPGA Family: Pinout Descriptions FG900 Footprint Left Half of FG900 Package (top view) XC3S2000 (565 max. user I/O) I/O: Unrestricted, 481 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N.C.: Unconnected pins for 68 ...
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R Bank I/O I/O I/O I/O L39N_1 I/O GND GND L26N_1 L21N_1 L15N_1 L11N_1 I/O I/O I/O I/O I/O I/O I/O L39P_1 L32N_1 L17N_1 L28N_1 L26P_1 L21P_1 L15P_1 L11P_1 VREF_1 GCLK5 I/O ...
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Spartan-3 FPGA Family: Pinout Descriptions FG1156: 1156-lead Fine-pitch Ball Grid Array Note: The FG(G)1156 package is being discontinued and is not recommended for new designs. See http://www.xilinx.com/support/documentation/ spartan-3_customer_notices.htm The 1,156-lead fine-pitch ball grid array package, FG1156, supports two different Spartan-3 ...
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R Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 0 IO_L17N_0 IO_L17N_0 0 IO_L17P_0 IO_L17P_0 0 IO_L18N_0 IO_L18N_0 0 IO_L18P_0 IO_L18P_0 0 IO_L19N_0 IO_L19N_0 0 IO_L19P_0 IO_L19P_0 0 IO_L20N_0 IO_L20N_0 0 IO_L20P_0 IO_L20P_0 0 IO_L21N_0 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 1 IO/VREF_1 IO/VREF_1 1 IO/VREF_1 IO/VREF_1 1 IO_L01N_1/ IO_L01N_1/ VRP_1 VRP_1 1 IO_L01P_1/ IO_L01P_1/ VRN_1 VRN_1 1 IO_L02N_1 IO_L02N_1 1 IO_L02P_1 IO_L02P_1 ...
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R Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 1 IO_L38N_1 IO_L38N_1 1 IO_L38P_1 IO_L38P_1 1 IO_L39N_1 IO_L39N_1 1 IO_L39P_1 IO_L39P_1 1 IO_L40N_1 IO_L40N_1 1 IO_L40P_1 IO_L40P_1 1 VCCO_1 VCCO_1 1 VCCO_1 VCCO_1 1 VCCO_1 ...
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Spartan-3 FPGA Family: Pinout Descriptions Table 109: FG1156 Package Pinout (Continued) XC3S4000 XC3S5000 Bank Pin Name Pin Name 2 IO_L30N_2 IO_L30N_2 2 IO_L30P_2 IO_L30P_2 2 IO_L31N_2 IO_L31N_2 2 IO_L31P_2 IO_L31P_2 2 IO_L32N_2 IO_L32N_2 2 IO_L32P_2 IO_L32P_2 2 IO_L33N_2 IO_L33N_2 2 ...