IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 56

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

Note 3: This bit no longer has a pin associated with it.
Note 4: These bits are always zero in the non-FIFO mode.
Note 5: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Data Bit 2
Data Bit 2
Enable Receiver
Line Status
Interrupt (ELSI)
Interrupt ID Bit
XMIT FIFO
Reset
Number of Stop
Bits (STB)
OUT1
(Note 3)
Parity Error (PE) Framing Error
Trailing Edge
Ring Indicator
(TERI)
Bit 2
Bit 2
Bit 10
BIT 2
Table 34 - Register Summary For An Individual UART Channel (continued)
Interrupt ID Bit
Data Bit 3
Data Bit 3
Enable MODEM
Status Interrupt
(EMSI)
(Note 4)
DMA Mode
Select (Note 5)
Parity Enable
(PEN)
OUT2
(Note 3)
(FE)
Delta Data
Carrier Detect
(DDCD)
Bit 3
Bit 3
Bit 11
BIT 3
Data Bit 4
Data Bit 4
0
0
Reserved
Even Parity
Select (EPS)
Loop
Break Interrupt
(BI)
Clear to Send
(CTS)
Bit 4
Bit 4
Bit 12
BIT 4
56
Data Bit 5
Data Bit 5
0
0
Reserved
Stick Parity
0
Transmitter
Holding Register
(THRE)
Data Set Ready
(DSR)
Bit 5
Bit 5
Bit 13
BIT 5
Data Bit 6
Data Bit 6
0
FIFOs Enabled
(Note 4)
RCVR Trigger
LSB
Set Break
0
Transmitter
Empty (TEMT)
(Note 2)
Ring Indicator
(RI)
Bit 6
Bit 6
Bit 14
BIT 6
Data Bit 7
Data Bit 7
0
FIFOs Enabled
(Note 4)
RCVR Trigger
MSB
Divisor Latch
Access Bit
(DLAB)
0
Error in RCVR
FIFO (Note 4)
Data Carrier
Detect (DCD)
Bit 7
Bit 15
Bit 7
BIT 7