ADP3211 ON Semiconductor, ADP3211 Datasheet - Page 15

• Manufacturer Part Number: ADP3211
• Description: 7-bit, Programmable, Single-phase, Synchronous Buck Controller
• Manufacturer: ON Semiconductor

VID Change and Soft Transient
a VID input changes, the ADP3211 detects the change but
ignores new code for a minimum of 400 ns. This delay is
required to prevent the device from reacting to digital
signal skew while the 7−bit VID input code is in transition.
Additionally, the VID change triggers a PWRGD masking
timer to prevent a PWRGD failure. Each VID change resets
and re−triggers the internal PWRGD masking timer.
reduce inrush current during VID transitions. Reducing the
inrush current helps decrease the acoustic noise generated
by the MLCC input capacitors and inductors.
When a new VID code is detected, the ADP3211 steps
sequentially through each VID voltage to the final VID
voltage.
With GPU connected to 5.0 V for GPU operation, when
The ADP3211 provides a soft transient function to
The soft transient feature is implemented internally.
V
PWRGD
GPU = 5.0 V
CCGFX
Figure 23. Powerup Sequence for GPU
V5_S
EN
GPU = 0 V
PGDELAY
Figure 22. ADP3211 Powerup Sequence for CPU
VCC = 5.0 V
EN
V
BOOT
= 1.1 V
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15
CLKEN
Current Limit, Short−Circuit, and Latchoff Protection
R
current limit set point to the voltage from the output of the
current sense amplifier. The level of current limit is set with
the resistor from the ILIM pin to CSCOMP. During
operation, the voltage on ILIM is equal to the voltage on
CSREF. The current through the external resistor
connected between I
the internal current limit current I
through this resistor into the ILIM pin (Ilim) exceeds the
internal current limit threshold current (I
current limit amplifier controls the internal COMP voltage
to maintain the average output current at the limit.
a current overload, the ADP3211 switches to PWM mode.
constant current mode to ensure that the external
MOSFETs and inductor function properly and to protect
the GPU or CPU. With a low constant impedance load, the
output voltage decreases to supply only the set current
limit. If the output voltage drops below the power−good
limit, the PWRGD signal transitions. After the PWRGD
single transitions, internal waits 8 ms before latching off
the ADP3211.
overload.
CLIM
The ADP3211 has an adjustable current limit set by the
Normally, the ADP3211 operates in RPM mode. During
With low impedance loads, the ADP3211 operates in a
Figure 24 shows how the ADP3211 reacts to a current
t
t
CPU_PWRGD
BOOT
DAC and V
resistor. The ADP3211 compares a programmable
PWRGD
CORE
LIM
and CSCOMP is then compared to
cl.
If the current generated
cl)
, the internal