SN74LS569N Motorola, SN74LS569N Datasheet - Page 3

• Manufacturer Part Number: SN74LS569N
• Description: FOUR-BIT UP/DOWN COUNTER WITH THREE-STATE OUTPUTS
• Manufacturer: Motorola

DEFINITION OF FUNCTIONAL TERMS
A, B, C, D
CEP
CET
CP
LOAD
U/D
The four programmable data inputs.
Count Enable Parallel. Can be used to
enable and inhibit counting in high speed
cascaded operation. CEP must be LOW to
count.
Count Enable Trickle. Enables the ripple
carry output for cascaded operation. Must
be LOW to count.
Clock Pulse. All synchronous functions
occur on the LOW-to-HIGH transition of the
clock.
Enables parallel load of counter outputs
from data inputs on the next clock edge.
Must be HIGH to count.
Up/Down Count Control. HIGH counts up
and LOW counts down.
V CC
DRIVING OUTPUT
LOW-POWER SCHOTTKY INPUT/OUTPUT
CURRENT INTERFACE CONDITIONS
I OH
I OL
Note: Actual current flow direction shown
FAST AND LS TTL DATA
SN54/74LS569A
DRIVING OUTPUT
5-575
ACLR
SCLR
OE
Y A , Y B , Y C , Y D The four counter outputs.
RCO
CCO
I OH I IL
I OL
I IH
Asynchronous Clear. Master reset of
counters to zero when ACLR is LOW,
independent of the clock.
Synchronous clear of counters to zero on
the next clock edge when SCLR is LOW.
A HIGH on the output control sets the four
counter outputs in the high impedance, and
a LOW, enables the output.
Ripple Carry Output. Output will be LOW on
the maximum count on up-count. Upon
down-count, RCO is LOW at 0000.
Clock Carry Output. While counting and
RCO is LOW, CCO will follow the clock
HIGH-LOW-HIGH transition.
DRIVEN INPUT