LM3S1110 Luminary Micro, Inc, LM3S1110 Datasheet - Page 127
LM3S1110
Manufacturer Part Number
LM3S1110
Description
Lm3s1110 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1110.pdf
(405 pages)
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Reset
Reset
Type
Type
Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type R/W1C, reset 0x0000.0000
July 25, 2008
Bit/Field
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
RO
RO
30
14
0
0
RTCALT1
RTCALT0
LOWBAT
reserved
RO
RO
29
13
0
0
EXTW
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
R/W1C
R/W1C
R/W1C
R/W1C
Type
RO
RO
RO
26
10
0
0
reserved
0x000.0000
Reset
RO
RO
25
0
9
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
External Wake-Up Masked Interrupt Clear
Reads return an indeterminate value.
Low Battery Voltage Masked Interrupt Clear
Reads return an indeterminate value.
RTC Alert1 Masked Interrupt Clear
Reads return an indeterminate value.
RTC Alert0 Masked Interrupt Clear
Reads return an indeterminate value.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
R/W1C
EXTW
LM3S1110 Microcontroller
RO
19
0
3
0
LOWBAT
R/W1C
RO
18
0
2
0
RTCALT1
R/W1C
RO
17
0
1
0
RTCALT0
R/W1C
RO
16
0
0
0
127
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