LM3S1439 Luminary Micro, Inc, LM3S1439 Datasheet - Page 494
![no-image](/images/no-image-200.jpg)
LM3S1439
Manufacturer Part Number
LM3S1439
Description
Lm3s1439 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1439.pdf
(544 pages)
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Signal Tables
494
Pin Name
I2C0SCL
I2C0SDA
CMOD1
Fault
GNDA
GNDA
IDX0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HIB
LDO
NC
NC
NC
NC
NC
NC
Pin Number
M12
C12
B10
L10
K10
F10
F12
C11
J10
F11
C4
C5
H3
K5
K6
B6
B5
A5
E3
A2
A3
B4
A4
D1
D2
F2
J3
F1
Preliminary
Pin Type
I/O
I/O
I/O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
I
Buffer Type
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
TTL
TTL
TTL
TTL
OD
OD
-
-
-
-
-
-
Description
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
PWM Fault
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
An output that indicates the processor is in
hibernate mode.
I2C module 0 clock
I2C module 0 data
QEI module 0 index
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDD25 pins
at the board level in addition to the decoupling
capacitor(s).
No connect. Leave the pin electrically
unconnected/isolated.
No connect. Leave the pin electrically
unconnected/isolated.
No connect. Leave the pin electrically
unconnected/isolated.
No connect. Leave the pin electrically
unconnected/isolated.
No connect. Leave the pin electrically
unconnected/isolated.
No connect. Leave the pin electrically
unconnected/isolated.
July 25, 2008
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