LM3S2139 Luminary Micro, Inc, LM3S2139 Datasheet - Page 16

• Manufacturer Part Number: LM3S2139
• Description: Lm3s2139 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Inter-Integrated Circuit (I
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Controller Area Network (CAN) Module ..................................................................................... 387
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
16
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 343
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 344
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 345
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 346
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 347
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 348
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 349
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 350
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 351
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CAN Control (CANCTL), offset 0x000 ............................................................................. 400
CAN Status (CANSTS), offset 0x004 ............................................................................... 402
CAN Error Counter (CANERR), offset 0x008 ................................................................... 405
CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 406
CAN Interrupt (CANINT), offset 0x010 ............................................................................. 408
CAN Test (CANTST), offset 0x014 .................................................................................. 409
CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 411
CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 412
CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 412
CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 413
CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 413
CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 416
CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 416
CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 417
CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 417
CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 418
CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 418
CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 419
CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 419
CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 421
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 366
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 367
C Master Data (I2CMDR), offset 0x008 ......................................................................... 371
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 372
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 373
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 374
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 375
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 376
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 377
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 379
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 380
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 382
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 383
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 384
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 385
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 386
2
C) Interface ........................................................................................ 352
Preliminary
July 25, 2008