LM3S2651 Luminary Micro, Inc, LM3S2651 Datasheet - Page 10

• Manufacturer Part Number: LM3S2651
• Description: Lm3s2651 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10. Master Burst RECEIVE .................................................................................................. 386
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 387
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 388
Figure 15-13. Slave Command Sequence ............................................................................................ 389
Figure 16-1.
Figure 16-2.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 18-1.
Figure 18-2.
Figure 18-3.
Figure 18-4.
Figure 18-5.
Figure 18-6.
Figure 19-1.
Figure 19-2.
Figure 22-1.
Figure 22-2.
Figure 22-3.
Figure 22-4.
Figure 22-5.
Figure 22-6.
Figure 22-7.
Figure 22-8.
Figure 22-9.
Figure 22-10. External Reset Timing (RST) .......................................................................................... 541
Figure 22-11. Power-On Reset Timing ................................................................................................. 542
Figure 22-12. Brown-Out Reset Timing ................................................................................................ 542
Figure 22-13. Software Reset Timing ................................................................................................... 542
Figure 22-14. Watchdog Reset Timing ................................................................................................. 542
Figure 23-1.
Figure 23-2.
10
START and STOP Conditions ......................................................................................... 379
Complete Data Transfer with a 7-Bit Address ................................................................... 380
R/S Bit in First Byte ........................................................................................................ 380
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 383
Master Single RECEIVE ................................................................................................. 384
Master Burst SEND ....................................................................................................... 385
CAN Module Block Diagram ........................................................................................... 414
CAN Bit Time ................................................................................................................ 421
Analog Comparator Module Block Diagram ..................................................................... 454
Structure of Comparator Unit .......................................................................................... 455
Comparator Internal Reference Structure ........................................................................ 456
PWM Unit Diagram ........................................................................................................ 465
PWM Module Block Diagram .......................................................................................... 466
PWM Count-Down Mode ................................................................................................ 467
PWM Count-Up/Down Mode .......................................................................................... 467
PWM Generation Example In Count-Up/Down Mode ....................................................... 468
PWM Dead-Band Generator ........................................................................................... 468
100-Pin LQFP Package Pin Diagram .............................................................................. 501
108-Ball BGA Package Pin Diagram (Top View) ............................................................... 502
Load Conditions ............................................................................................................ 534
I
Hibernation Module Timing ............................................................................................. 537
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 538
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 538
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 539
JTAG Test Clock Input Timing ......................................................................................... 540
JTAG Test Access Port (TAP) Timing .............................................................................. 540
JTAG TRST Timing ........................................................................................................ 540
100-Pin LQFP Package .................................................................................................. 543
108-Ball BGA Package .................................................................................................. 545
2
C Timing ..................................................................................................................... 537
Preliminary
2
C Bus ............................................................... 380
July 25, 2008