CLA80000 Zarlink Semiconductor, CLA80000 Datasheet

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CLA80000

Manufacturer Part Number
CLA80000
Description
High Density CMOS Gate Arrays
Manufacturer
Zarlink Semiconductor
Datasheet
www.DataSheet4U.com
( DataSheet : www.DataSheet4U.com )
INTRODUCTION
The CLA80k gate array series from Zarlink Semiconductor
offers advantages in speed and density over previous array
series. Improvements in design combined with advances in
simulation accuracy allow the implementation of complex
systems in excess of 260,000 gates.
FEATURES
I 0.7 µ (0.8 µ drawn) process
I Typical gate delay 210ps
I Accurate simulation delay (multi platform support)
I Support for industry standard workstations
I Comprehensive cell library
I 3V option for low power operation
I Split rail operation (optional 5V I/O, 3V core logic)
I Low skew clock distribution strategy
I Power and ground distribution grids
I Extensive range of package options
OVERVIEW
The gate array has a comprehensive cell library including
RAM generators as well as JTAG circuits. CLA80k is Zarlink
Semiconductor’s seventh generation CMOS gate array
product. The family consists of 22 arrays implemented on a
proven 0.7 µ m (0.8 µ m drawn) process which offers two or
three layer metal.
Zarlink Semiconductor’s Design Centres offer support on a
variety of design routes customized to individual
requirements.
Zarlink supplies design kits for the major industry standard
ASIC design tools and all kits support advanced nonlinear
delay calculations essential for accurate simulation.
Standard Density Pad Arrays are targeted for use in
ceramic packaging and for those applications which require
assembly in conformance with MIL STD 883.
ARRAY SIZES
The CLA80k series comprises 9 base arrays and 22
variants ranging from 2816 to 513,136 array elements. The
optimum array for your requirement may be selected from
the tables below.
Double Layer Metal Arrays (High Density Pads)
Triple Layer Metal Arrays (High Density Pads)
Standard Density Pad Arrays
Array type
CLA81XXX
CLA82XXX
CLA83XXX
CLA84XXX
CLA85XXX
CLA86XXX
CLA87XXX
Array type
CLT81XXX
CLT82XXX
CLT83XXX
CLT84XXX
CLT85XXX
CLT86XXX
CLT87XXX
CLT88XXX
CLT89XXX
Array type
MLA85XXX
MLT85XXX
MLA87XXX
MLT87XXX
MLT88XXX
MLT89XXX
DS3820
High Density CMOS Gate Arrays
Array
elements
Array
elements
Array
elements
100048
157872
100048
157872
307568
513136
157872
157872
307568
513136
17920
30784
54720
17920
30784
54720
54720
54720
2816
8736
2816
8736
CLA80000 Series
ISSUE 2.1
Usable
gates
Usable
gates
Usable
gates
170000
260000
170000
260000
13600
22000
30000
48000
10700
18000
32500
58000
90000
22000
32500
48000
90000
1400
4260
8400
1680
5200
www.DataSheet4U.com
Total
Pads
Total
pads
Total
pads
112
136
168
216
264
112
136
168
216
264
360
456
144
144
232
232
312
384
64
88
64
88
July 1997

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CLA80000 Summary of contents

Page 1

... Standard Density Pad Arrays are targeted for use in ceramic packaging and for those applications which require assembly in conformance with MIL STD 883. www.DataSheet4U.com CLA80000 Series High Density CMOS Gate Arrays DS3820 ISSUE 2.1 ARRAY SIZES The CLA80k series comprises 9 base arrays and 22 variants ranging from 2816 to 513,136 array elements ...

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ARCHITECTURE Core cell I Optimized structure for a variety of logic elements I Allows routing through cells for compact layout The basic unit from which all library functions are constructed is called an ‘array element’. An array element consists of ...

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CLOCK AND POWER DISTRIBUTION I Low skew clock distribution strategy I Power grid to minimize voltage drop In large complex designs working at high speed, on chip clock and power distribution is vital to successful operation of the design. Zarlink ...

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CELL LIBRARY I Comprehensive range of cells I JTAG and Paracell libraries A comprehensive cell library is available for the CLA80k series. It contains libraries that may be used in specific applications areas such JTAG boundary scan. Buffers and Inverters ...

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Clock Grid Drivers CLKB84 Clock Grid Driver for CLT84000 CLKB85 Clock Grid Driver for CLT85000, MLT85000 CLKB86 Clock Grid Driver for CLT86000 CLKB87 Clock Grid Driver for CLT87000, MLT87000 CLKB88 Clock Grid Driver for CLT88000, MLT88000 CLKB89 Clock Grid Driver ...

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DESIGN SUPPORT Design Route I Flexible design route I Proven right first time design Design and layout support for the CLA80k arrays is available from many centres worldwide each of which is connected to our headquarters via high speed data ...

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SOFTWARE TOOLS Concept Assessment Design capture/compilation or synthesis Testability analysis INDUSTRY STANDARD DESIGN Functional simulation SOFTWARE AND Zarlink LIBRARIES vectors simulation Zarlink VERIFICATION Netlist handover TOOLS Zarlink OR Place and INDUSTRY- route STANDARD LAYOUT TOOLS Post-layout simulation INDUSTRY- STANDARD SOFTWARE ...

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THERMAL MANAGEMENT I Low power CMOS for better thermal management I 1.3 µ W per gate per MHz (3V supply) I High pinout power packages available The increase in speed and density available through advanced CMOS processes, results in a ...

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Cell 8 stage ripple carry adder 8 stage ripple carry adder 10 NAND2 gates, lightly loaded 10 NAND2 gates mixed heavy then light loading 10 NAND2 gates heavy loading 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 ...

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Derating for Supply Voltage Figure 9 shows the increase in gate delay as supply voltage is reduced. 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 2.5 Derating for Temperature Figure 10 shows the increase in gate delay ...

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AC ELECTRICAL CHARACTERISTICS GATES tpLH INVX1 tpHL tpLH NAND2X2 tpHL tpLH NOR2x2 tpHL tpLH DF tpHL INPUTS tpLH TTL I/P tpHL tpLH CMOS I/P tpHL tpLH CMOS SCHMITT tpHL OUTPUT tpLH 6mA BISTATE tpHL tpLH 12mA BISTATE tpHL tpLH 24mA ...

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ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Input Voltage Output Voltage Static discharge voltage (HBM) Storage Temperature Ceramic Plastic Exceeding the absolute maximum ratings may cause permanent damage to the device. Extended exposure at the maximum ratings will affect device reliability. ...

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Input Characteristics Characteristic Sym TTL input - IBTTL1 V Input low voltage IL V Input high voltage IH TTL input - IBTTL2 V Input low voltage IL V Input high voltage IH CMOS input - IBCMOS1 V Input low voltage ...

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Output Characteristics Characteristic Sym High output voltage V All outputs OH V OPT1 OH V OPT2 OH V OPT3 OH V OPT6 OH V OPT12 OH Low output voltage V All outputs OL V OPT1 OL V OPT2 OL V ...

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Characteristic Sym Tristate output leakage I OPT1 OZ I OPT2 OZ I OPT3 OZ I OPT6 OZ I OPT12 OZ Tristate output leakage I OPT1 OZ I OPT2 OZ I OPT3 OZ I OPT6 OZ I OPT12 OZ Output short ...

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QUALITY AND RELIABILITY I Statistical process control used in manufacture I Regular sample screening and reliability testing I Screening to MIL and other recognized standards At Zarlink quality and reliability are built into the product by statistical control of all ...

Page 17

HIGH DENSITY PAD ARRAY PRODUCTION PACKAGING OPTIONS Style Leads Code Pitch MQFP44-GP- 44 0.80 1010 MQFP52-GP- 52 0.65 1010 MQFP64- GP- 64 1.00 1420 MQFP64-GP 0.80 1414 MQFP64-GP 0.80 1414 MQFP80-GP 0.80 1420 MQFP80-GQ- ...

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LQFP144-FP- P 144 0.50 2020 LQFP176-FP- 176 0.50 2424 Style Leads Code Pitch PLCC28-HP 1.27 1212 PLCC44-HP 1.27 1717 PLCC68-HP 1.27 2525 PLCC84-HP 1.27 3030 Style Leads Code Pitch PSOP16-MP ...

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HIGH DENSITY PAD ARRAY PROTOTYPING PACKAGING OPTIONS Important: CQFP/CSOP is for prototyping only not available for production. Style Leads Code Pitch CQFP44-GG- 44 0.80 1010 CQFP52-GG- 52 0.65 1010 CQFP64- GG- 64 1.00 1420 CQFP64-GG 0.80 ...

Page 20

Style Leads Code Pitch CcLCC28-HC 1.27 1212 CcLCC44-HC 1.27 1717 CcLCC68-HC 1.27 2525 CcLCC84-HC 1.27 3030 C Style Leads Code Pitch CSOP16-MC 1.27 0811 CSOP20-MC 1.27 0813 CSOP24-MC- ...

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STANDARD DENSITY PAD ARRAY PACKAGING OPTIONS, MILITARY ARRAYS Style Leads Code C 68 CcLCC68-HC-2525 c 84 CcLCC84-HC-3030 Style Leads Code L 132 LdCC132-GCA-2424 d 172 LdCC172-GCA-3030 C 196 LdCC196-GCA-3535 C Style Leads Code L 132 LdCC132-GCP-2424 d ...

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NOTES ...

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NOTES 23 ...

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... Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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