CLAA170EA07P CHUNGHWA PICTURE TUBES, CLAA170EA07P Datasheet - Page 11

• Manufacturer Part Number: CLAA170EA07P
• Description: Display Module
• Manufacturer: CHUNGHWA PICTURE TUBES

CPT
5. INTERFACE TIMING
CPT Confidential
(1) Timing Specifications
[Note]
Timing
LCD
1) DENA should always be positive polarity as shown in the timing specification.
2) CLK INshould appear during all blanking period,
3) Using LVDS IC
4) Required signal assignment for flat link transmitter
Pin No. Pin Name
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Receiver
DS90C384MTD(NS)
SN75LVDS82(TI)
1
2
3
4
5
6
7
8
9
DCLK
DENA
GND
GND
GND
VCC
VCC
VCC
VCC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D5
D6
D7
D8
D9
Frequency
Period
Horizontal Active Time
Horizontal Blank Time
Horizontal Total Time
Vertical Active Time
Vertical Blank Time
Vertical Total Time
Vertical Frame Rate
ITEM
Power Supply for TTL Input
Power Supply for TTL Input
Power Supply for TTL Input
Power Supply for TTL Input
TTL Input (HSYNC)
TTL Input (VSYNC)
Ground pin for TTL
Ground pin for TTL
Ground pin for TTL
TTL Input (LVDS)
Require Signal
TTL Input (G7)
TTL Input (G5)
TTL Input (R7)
TTL Input (R5)
TTL Input (G0)
TTL Input (G1)
TTL Input (G2)
TTL Input (G6)
TTL Input (G3)
TTL Input (G4)
TTL Input (B0)
TTL Input (B6)
TTL Input (B7)
TTL Input (B1)
TTL Input (B2)
TTL Input (B3)
TTL Input (B4)
TTL Input (B5)
Transmitter
DS90C383MTD(NS)
SN75LVDS83(TI)
11/22
SYMBOL
f
t
t
t
t
t
CLK
CLK
Fr
HA
t
VA
t
HB
VB
Pin No.
H
V
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
www.DataSheet.net/
TxCLKOUT+
CLAA170EA07P Y-STUDIO-2008/08/05
MIN
TxCLKOUT-
1024
1046
CHUNGHWA PICTURES TUBES, LTD.,
14.3
LVDS GND
LVDS GND
LVDS GND
LVDS VCC
640
112
752
PWR DWN
45
22
55
Pin Name
TxCLKIN
PLL GND
PLL GND
TxOUT3+
TxOUT2+
TxOUT1+
TxOUT0+
PLL VCC
TxOUT3-
TxOUT2-
TxOUT1-
TxOUT0-
GND
GND
D26
D27
D0
D1
D2
D3
D4
TYP
1024
1066
18.5
640
204
844
54
42
60
Negative LVDS differential data output 3
Negative LVDS differential data output 2
Negative LVDS differential data output 1
Negative LVDS differential data output 0
Negative LVDS differential clock output
Positive LDVS differential data output 2
Positive LVDS differential data output 0
Positive LVDS differential data output 3
Positive LVDS differential data output 1
Positive LVDS differential clock output
Power Supply for LVDS
MAX
TTL Level clock Input
Power Supply for PLL
1030
1024
1100
Ground pin for LVDS
Ground pin for LVDS
22.2
640
390
Ground pin for TTL
Ground pin for TTL
Ground pin for TTL
www.yslcd.com.tw
Ground pin for PLL
Ground pin for PLL
70
76
75
Power Down Input
Require Signal
TTL Input (R6)
TTL Input (R0)
TTL Input (R1)
TTL Input (R2)
TTL Input (R3)
TTL Input (R4)
TTL Input(DE)
UNIT
MHz
t
t
t
Hz
CLK
CLK
CLK
ns
t
t
t
H
H
H
Datasheet pdf - http://www.DataSheet4U.co.kr/