NE5562D Philipss, NE5562D Datasheet - Page 18

• Manufacturer Part Number: NE5562D
• Description: Switched-mode power supply control circuit
• Manufacturer: Philipss

Philips Semiconductors
DUAL-LEVEL OVERCURRENT COMPARATORS
The overcurrent sensing circuit (Figure 29) consists of a single PNP
input buffer with emitter-follower tied to V
base of an NPN split-emitter transistor. This forms the input node to
a set of dual-level voltage comparators with references of 0.528 and
0.645V, respectively. Current sources for the comparator are fixed
biased NPNs.
The typical transition time delay for an overcurrent fault is 300ns.
Bias current at the input averages 500nA.
1994 Aug 31
Switched-mode power supply control circuit
NE/SE5562
+V
CC
Figure 30. Transient Suppression
C
F
10% CARBON
REFERENCE
REFERENCE
500-1000
0.645V
0.528V
Z
, 7.50V, feeding into the
Figure 29. NE/SE5562 Overcurrent Comparator
I
MAG
R
SH
135 A
135 A
100 A
SL00417
3k
1.5V
V
3k
Z
1.5V
= 7.50V
OC2
OC1
18
100 A
If the overcurrent sense feature is not used, it is recommended that
Pin 14 be tied to ground.
When used for sensing current-derived voltage impulses from the
primary driver, a high-speed, low-impedance transient filter network
is advised. An example is shown in Figure 30. Keep C
NE/SE5562.
THEORY—OC1 AND OC2
Overcurrent Logic and Delay Capacitor Operations
The circuit takes a voltage input from Pin 14 and compares the level
to a dual reference comparator with trips at 0.53 and 0.65V. The
lower trip point actuates cycle-by-cycle shutdown of the output stage
with an intrinsic delay of 400ns. The second level actuates the
slow-start function. In addition, there exists a separate
housekeeping circuit whose function is to terminate operation of the
output stage if its threshold is exceeded. This involves a time delay
circuit based on two separate switchable current sources, OC1 and
OC2. The time delay capacitor allows the user to program shutdown
of the system after a predetermined number of overcurrent cycles
have occurred within the period set by the ramp-up of the delay
capacitor. Once shutdown has occurred in this manner, external
reset is required to restart the system. Referring to the logic block
Figure 31, which controls the gating of the two charge pumps into
the delay capacitor at Pin 16, the complete signal flow may be
traced. Logic signals from the overcurrent 1 and 2 comparators are
gated by the clock and delayed clock signals generated by the
135 A
0.528V
14
135 A
CURRENT
SENSE
INPUT
0.645V
NE/SE5562
Product specification
F
close to the
SL00416