CS8416-IS Cirrus Logic, CS8416-IS Datasheet
CS8416-IS
Related parts for CS8416-IS
CS8416-IS Summary of contents
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... CS8416 with dedicated output pins for channel status data. Target applications include A/V receivers, CD-R, DVD receivers, multimedia speakers, digital mixing consoles, effects processors, set-top boxes, and computer and au- tomotive audio systems. ORDERING INFORMATION CS8416-CS CS8416-CZ CS8416-IS CS8416-IZ VD+ VL+ DGND RMCK De-emphasis Filter Clock & AES3 C & ...
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... IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners format................................................................. 9 CS8416 DS578PP2 ...
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... Interrupt 1 Status (0Dh) ................................................................................................. 32 8.14 Q-Channel Subcode (0Eh - 17h) .................................................................................... 32 8.15 OMCK/RMCK Ratio (18h) .............................................................................................. 33 8.16 Channel Status Registers (19h - 22h) ............................................................................ 33 8.17 IEC61937 PC/PD Burst preamble (23h - 26h)................................................................ 33 8.18 CS8416 I.D. and Version Register (7Fh) ........................................................................ 33 8.19 Memory Address Pointer (MAP) ..................................................................................... 34 9. PIN DESCRIPTION - SOFTWARE MODE ............................................................................ 35 10 HARDWARE MODE .............................................................................................................. 37 10.1 Serial Audio Port Formats ............................................................................................. 37 11 PIN DESCRIPTION - HARDWARE MODE ...
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... Figure 18. TTL/CMOS Input Circuit............................................................................................... 46 Figure 19. Channel Status Data Buffer Structure .......................................................................... 47 Figure 20. Flowchart for Reading the E Buffer .............................................................................. 47 LIST OF TABLES Table 1. Delays by Frequency Values ................................................................................................. 14 Table 2. External PLL Component Values........................................................................................... 17 Table 3. GPO Pin Configurations ........................................................................................................ 22 Table 4. Hardware Mode Serial Audio Format Select ......................................................................... Mode .................................................................................. 21 CS8416 DS578PP2 ...
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... Ambient Operating Temperature Notes: 4. Transient currents 100mA will not cause SCR latch-up. DS578PP2 Symbol VA+ VD+ VL (Note (Note ‘-IS’ & ‘-IZ’ (Note 3) Symbol VD+, VA+, VL CS8416-C CS8416-I CS8416 Min Typ Max 3.13 3.3 3.46 3.13 3.3 3.46 3.13 3.3 5 ...
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... V -0 ( -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = VD+ = 3.3 V ± 5%, VL+ = 3.135 pF) L Symbol Min 200 CS8416 Typ Max Units - (VL+)+0.3 Volts - 0.8 Volts - 0.5 Volts - VL+ Volts - 1.0 Volts - 10 uA 150 200 mV Typ Max Units ...
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... OLRCK (input) t OSCLK (input SDOUT Figure 2. Audio Port Slave Mode and Data Input Timing CS8416 Min Typ Max - - lrckd ...
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... Figure 3. SPI Mode Timing CS8416 Min Max Unit 0 6.0 MHz 1.0 - µ 100 ...
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... Repeated Start t high t t sud t sust hdd 2 Figure Mode Timing CS8416 2 C FORMAT = 20 pF) L Min Max Unit - 100 kHz 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ 250 - ...
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... RXP3 RXP4 RMCK RXP5 RXP6 OMCK RXP7 GPO0 AD0 / CS GPO1 AD1 / CDIN AD2/GPO2 SCL / CCLK SDA / CDOUT RST AGND FILT DGND Rflt Cflt Crip *** CS8416 +3.3V to +5V µ 0.1 F 1nF 47KΩ Serial Audio Input Device Clock Control Clock Source External Interface DS578PP2 ...
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... OSCLK RXP0 SDOUT RXP1 CS8416 RXP2 RXP3 RST RXSEL0 RXSEL1 RMCK TXSEL0 TXSEL1 OMCK * NV/RERR * AUDIO 96KHZ * TX * RCBL * AGND FILT DGND Rflt Cflt Crip **** CS8416 +3.3V to +5V µ 0.1 F 1nF Serial Audio Input Device 47KΩ Clock Control Clock Source External Interface 11 ...
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... GENERAL DESCRIPTION The CS8416 is a monolithic CMOS device which receives and decodes audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 inter- face standards. The CS8416 utilizes an 8:2 multiplexer to select between eight inputs for decoding and to allow an input signal to be routed to an output of the CS8416 ...
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... OSCLK can be asynchronous and discontinu- ous if required. By appropriate phasing of OLRCK and control of the serial clocks, multiple CS8416’s can share one serial port. OLRCK should be con- tinuous, but the duty cycle can be less than the ...
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... INT will be equal to the difference in frequency between the input AES data and the slave serial output LRCK. The CS8416 uses a hys- teresis window when a slip/repeat event occurs. The slip/repeat is triggered when an edge of OL- RCK passes a window size from the beginning of the Z/X preamble ...
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... MSB Left MSB LSB MSB Extended MSB Extended Left LSB SOSF* SORES[1:0]* SOJUST CS8416 LSB MSB LSB MSB Right MSB LSB MSB Ex Right MSB LSB SODEL* SOSPOL* SOLRPOL ...
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... RXP[0-7] and a shared RXN. Single ended sig- 16 nals are accommodated by using RXP inputs and AC coupling RXN to ground. All inputs to the CS8416 8:2 input multiplexer should be coupled through a capacitor. The recom- mended capacitor value is 0.01uF to 0.1uF. The recommended dielectrics are COG or X7R. ...
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... Error Reporting and Hold Function Software Mode While decoding the incoming AES3 data stream, the CS8416 can identify several kinds of error, in- dicated in the Receiver Error register (0Ch). The errors indicated are: 1) QCRC – CRC error in Q subcode data 2) CCRC – CRC error in channel status data 3) UNLOCK – ...
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... CS8416. However, certain non-audio sources, such as AC-3 or MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8416 AES3 receiver can detect such non-audio data through the use of an autode- tect module. The autodetect module is similar to ...
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... The exception is the use of de-emphasis auto-select feature which will bypass the de-em- phasis filter if the input stream is detected to be non-audio the user to mute the outputs as required. Figure 9. C/U data outputs ± 50us T2 =15us F1 F2 3.183 10.61 Figure 10. De-emphasis filter CS8416 Frequency, KHz 19 ...
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... The control port has 2 modes: SPI and I CS8416 acting as a slave device in both modes. SPI mode is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been 2 brought high ...
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... The GPO2 pin is used to set the AD2 bit by connecting a 47K resistor from the GPO2 pin to VL DGND. The state of the pin is sensed while the CS8416 is being reset. The upper 4 bits of the 7-bit address field are fixed at 0010. To com- municate with a CS8416, the chip address field, ...
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... Notes: 13. Frequency = 25 MHz Max, duty cycle not guaranteed, target duty cycle = 50 6.4 Interrupts The CS8416 has a comprehensive interrupt capa- bility. The INT pin may be set to be active low, ac- tive high or active low with no active pull-up transistor. This last mode is used for active low, ...
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... BC0[5] BC0[4] BC1[7] BC1[6] BC1[5] BC1[4] BC2[7] BC2[6] BC2[5] BC2[4] BC3[7] BC3[6] BC3[5] BC3[4] BC4[7] BC4[6] BC4[5] BC4[4] PC0[7] PC0[6] PC0[5] PC0[4] CS8416 TRUNC Reserved Reserved HOLD1 HOLD0 RMCKF CHS GPO0SE GPO0SE GPO0SE GPO0SE GPO2SE GPO2SE GPO2SE ...
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... R ID & Version PC1[7] PC1[6] PC1[5] PC1[4] PD0[7] PD0[6] PD0[5] PD0[4] PD1[7] PD1[6] PD1[5] PD1[4] ID3 ID2 ID1 ID0 CS8416 PC1[3] PC1[2] PC1[1] PC1[0] PD0[3] PD0[2] PD0[1] PD0[0] PD1[3] PD1[2] PD1[1] PD1[0] VER3 VER2 VER1 VER0 DS578PP2 ...
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... HOLD[1:0] – Determine how received audio sample is affected when a receive error occurs Default = “00” 00 – hold last audio sample 01 – replace the current audio sample with 00 (mute) 10- do not change the received audio sample 11 - reserved DS578PP2 INT0 HOLD1 CS8416 TRUNC Reserved Reserved HOLD0 RMCKF CHS 25 ...
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... GPO0SEL[3:0] – GPO0 Source select. See GPO section in main text for settings table. Default = 0000 8.4 Control3 (03h GPO1SEL3 GPO1SEL2 GPO1SEL1 control port mode since an external resistor is re GPO1SEL0 GPO2SEL3 CS8416 GPO0SEL2 GPO0SEL1 GPO0SEL0 2 1 GPO2SEL2 GPO2SEL1 GPO2SEL0 DS578PP2 0 ...
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... Internal clocks are stopped. Internal state machines are reset. The fully static control port is oper- ational, allowing registers to be read or changed. Power consumption is low Normal part operation. This bit must be written to the 1 state to allow the CS8416 to begin opera- tion. All input clocks should be stable in frequency and phase when RUN is set to 1. ...
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... SOSPOL - OSCLK clock polarity Default = ‘0’ SDOUT sampled on rising edges of OSCLK 1 - SDOUT sampled on falling edges of OSCLK SOLRPOL - OLRCK clock polarity Default = ‘0’ SDOUT data is for the left channel when OLRCK is high 1 - SDOUT data is for the right channel when OLRCK is high 28 CS8416 DS578PP2 ...
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... Falling edge active 10 - Level active 11 - Reserved DS578PP2 UNLOCKM DETCM CCHM Interrupt Status DETC1 CCH1 DETC0 CCH0 CS8416 CONFM BIPM PARM RERRM QCHM FCHM register mask bit is set to 1, the Interrupt Status register RERR1 QCH1 FCH1 ...
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... Note: PCM, DTS_LD, DTS_CD and IEC61937 are mutually exclusive. PCM – Uncompressed PCM data was detected IEC61937 – IEC61937 data was detected DTS_LD – DTS_LD data was detected AUX0 PRO DTS_LD DTS_CD CS8416 COPY ORIG EMPH Reserved DGTL_SIL 96KHZ DS578PP2 ...
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... BIP - Bi-phase error bit. Updated on sub-frame boundaries error 1 - Bi-phase error. This indicates an error in the received bi-phase coding. PAR - Parity bit. Updated on sub-frame boundaries error 1 - Parity error DS578PP2 UNLOCK V CS8416 CONF BIP PAR 31 ...
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... DETC CCH CONTROL ADDRESS TRACK TRACK INDEX INDEX MINUTE MINUTE SECOND SECOND FRAME FRAME ZERO ZERO ABS FRAME ABS FRAME CS8416 RERR QCH FCH ADDRESS ADDRESS ADDRESS TRACK TRACK TRACK INDEX INDEX INDEX MINUTE MINUTE MINUTE SECOND ...
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... Channel B Status Byte 3 34 Channel B Status Byte 4 8.17 IEC61937 PC/PD Burst preamble (23h - 26h) 35 Burst Preamble PC Byte 0 36 Burst Preamble PC Byte 1 37 Burst Preamble PD Byte 0 38 Burst Preamble PD Byte 1 8.18 CS8416 I.D. and Version Register (7Fh ID3 ID2 ID1 ID[3:0]= 0010 VER[3:0] = 0001 (revision A) DS578PP2 ORR4 ORR3 > ...
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... Memory Address Pointer (MAP INCR MAP6 MAP5 INCR - Auto Increment Address Control Bit Default = ‘0’ Disabled 1 - Enabled MAP6:MAP0 - Register address MAP4 MAP3 MAP2 CS8416 1 0 MAP1 MAP0 DS578PP2 ...
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... Positive Analog Power - Positive supply for the analog section. Nominally +3.3 V. This supply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered clock Positive Digital Power – Nominally 3.3 V VD+ 23 Positive – Interface Power – 3 5.0 V: this supply sets the CS8416 I/O levels, including RXPx & VL+ 21 RXN AGND 6 Analog Ground - Ground for the analog circuitry in the chip ...
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... RST 9 Reset ( Input ) - When RST is low, the CS8416 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. AD0/CS 14 Address Bit 0 (I CS8416 into SPI control port mode ...
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... HARDWARE MODE The CS8416 has a hardware mode which allows using the device without a microcontroller. Hardware mode is selected by connecting the 47K pull-up/down resistor on the SDOUT pin to ground. Various pins change function in hardware mode, described in the hardware mode pin definition section (Section 11). ...
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... PLL Filter Pin – network should be connected from this pin to AGND. For best PLL jitter performance, this pin should be returned directly to the AGND pin RST 9 RESET(Input) – active low input . Resets CS8416 to default state, configuration pins are read on the rising edge of this pin NV/RERR 14 ...
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... Recovered Master Clock ( Output ) - Recovered master clock output when PLL is locked to the incoming AES3 stream. Frequency is 128/256x the sample rate (Fs). DS578PP2 if input sample rate is ≤ 48 KHz, ouputs a “0”. Outputs a “1” Output Indicates the beginning of a received channel status CS8416 39 ...
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... Hardware Mode Function Selection Hardware Mode and several options for that mode are selected by pulling CS8416 pins up or down imme- diately after RST is released. 1) SDOUT – Hardware/Software Mode select 2) RCBL – Serial Port slave/master select 3) NV/RERR – NVERR/RERR select 4) AUDIO – Serial Port Format select[1] (0/ – ...
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... Control Register 6 – Receiver Error Mask {QCRCM,CRCM {UNLOCKM,CONFM,BIPM,PARM} = 1111 VM set by pullup/pulldown on NV/RERR select Control Register 7 - Interrupt Status Mask N/A Control Register 8,9 - Interrupt Mode N/A DS578PP2 SOSF SORES[1:0] SOJUST SODEL SOSPOL SOLRPOL CS8416 ...
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... APPLICATIONS 12.1 Reset, Power Down and Start-up When RST is low, the CS8416 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are mut- ed. In Software Mode, when RST is high, the con- trol port becomes operational and the desired settings should be loaded into the control registers ...
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... L 0.016 ∝ 0° DS578PP2 D INCHES NOM MAX 0.098 0.104 0.008 0.012 0.017 0.020 0.011 0.013 0.705 0.713 17.70 0.295 0.299 0.050 0.060 0.407 0.419 10.00 0.026 0.050 4° 8° JEDEC #: MS-013 Controlling Dimension is Millimeters CS8416 MILLIMETERS MIN NOM MAX 2.35 2.50 2.65 0.10 0.20 0.30 0.33 0.42 0.51 0.23 0.28 0.32 17.90 18.10 7.40 7.50 7.60 1.02 1.27 1.52 10.34 10.65 0.40 ...
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... SEATING PLANE SIDE VIEW MAX MIN -- 0.47 -- 0.006 0.05 0.04 0.80 0.012 0.19 0.386 BSC 9.60 BSC 0.256 6.30 0.177 4. 0.029 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. CS8416 1 E1 END VIEW L MILLIMETERS NOTE NOM MAX -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 2,3 9.70 BSC 9.80 BSC 6.40 6.50 4.40 4.50 0.65 BSC -- 0.60 0.75 4° 8° DS578PP2 ∝ ...
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... APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS 14.1 AES3 Receiver External Components The CS8416 AES3 receiver is designed to accept both the professional and consumer interfaces. The digital audio specifications for professional use call for a balanced receiver, using XLR connectors, with 110 Ω ±20% impedance. The XLR connector on the receiver should have female pins with a male shell ...
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... RXN0 Coax Figure 17. S/PDIF MUX Input Circuit 0.01 µF Gate 0.01 µF Figure 18. TTL/CMOS Input Circuit CS8416 CS8416 µ 0. See Text RXP0 110 Ω µ 0.01 F RXN0 .01µF CS8416 RXP7 75 Ω .01µF RXP6 . 75 Ω .01µF RXP0 75 Ω RXN0 .01µF CS8416 RXP0 RXN0 DS578PP2 ...
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... E data without having to inhibit the next transfer. 15.2.1 Serial Copy Management System (SCMS) In software mode, the CS8416 allows read access to all the channel status bits. For consumer mode SCMS compliance, the host microcontroller needs to read and interpret the Category Code, Copy bit and L bit appropriately ...
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