IMX29F002 Macronix International, IMX29F002 Datasheet - Page 7

• Manufacturer Part Number: IMX29F002
• Description: 2M-BIT [256K x 8] CMOS FLASH MEMORY
• Manufacturer: Macronix International

READ/RESET COMMAND
The read or reset operation is initiated by writing the read/
reset command sequence into the command register.
Microprocessor read cycles retrieve array data. The
device remains enabled for reads until the command
register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid command
must then be written to place the device in the desired
state.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible while
the device resides in the target system.
programmers typically access signature codes by raising
A9 to a high voltage. However, multiplexing high voltage
onto address lines is not generally desired system design
practice.
The MX29F002T/B contains a Silicon-ID-Read operation
to supplement traditional PROM programming methodol-
ogy. The operation is initiated by writing the read silicon
ID command sequence into the command register. Fol-
lowing the command write, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer code of C2H. A read
cycle with A1=VIL, A0=VIH returns the device code of B0h
for MX29F002T, 34h for MX29F002B.
TABLE 3. EXPANDED SILICON ID CODE
P/N: PM0547
Manufacture code
Device code
for MX29F002T
Device code
for MX29F002B
Sector Protection
Verification
Pins A0 A1 Q7 Q6 Q5
VIH VIL
VIH VIL
VIL VIL
X VIH
X VIH
1
1
0
0
0
1
0
0
0
0
PROM
0
1
1
0
0
Q4
0
1
1
0
0
7
Q3 Q2 Q1 Q0
0
0
0
0
0
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device to
be entirely pre-programmed prior to executing the Auto-
matic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify the
entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the Read
mode. The system is not required to provide any control
or timing during these operations.
When using the Automatic Chip Erase algorithm, note that
the erase automatically terminates when adequate erase
margin has been achieved for the memory array(no erase
verify command is required).
If the Erase operation was unsuccessful, the data on Q5
is "1"(see Table 4), indicating the erase operation exceed
internal timing limit.
The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time the
device returns to the Read mode.
0
0
1
0
0
MX29F002/002N
1
0
0
0
0
0
0
0
1
0
Code(Hex)Code
01H (Protected)
00H (Unprotected)
C2H
B0h
34h
REV. 1.1, JUN. 14, 2001