CY7C4211V-15AC Cypress Semiconductor Corp, CY7C4211V-15AC Datasheet
CY7C4211V-15AC
Specifications of CY7C4211V-15AC
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CY7C4211V-15AC Summary of contents
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... Low-Voltage 64/256/512/1K/2K/4K/ Synchronous FIFOs Features • High-speed, low-power, first-in, first-out (FIFO) memories • (CY7C4421V) • 256 x 9 (CY7C4201V) • 512 x 9 (CY7C4211V) • (CY7C4221V) • (CY7C4231V) • (CY7C4241V) • (CY7C4251V) • High-speed 66-MHz operation (15-ns read/write cycle time) • Low power (I ...
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... Document #: 38-06010 Rev. *A CY7C42X1V-15 66 Commercial 20 CY7C4211V CY7C4221V 512 Data Inputs for 9-bit bus. O Data Outputs for 9-bit bus. I The only write enable when device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH ...
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Architecture The CY7C42X1V consists of an array words of nine bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and ...
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... LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4421V (64 – m), CY7C4201V (256 – m), CY7C4211V (512 – m), CY7C4221V (1K – m), CY7C4231V (2K – m), CY7C4241V (4K – m), and CY7C4251V (8K – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m ...
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... WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN1 and REN2 synchronized to RCLK, i.e exclusively updated by each rising edge of RCLK. CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V CY7C4211V FF PAF ...
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RESET (RS) DATA IN ( WRITE CLOCK (WCLK) WRITE ENABLE 1 (WEN1) WRITE ENABLE 2/LOAD (WEN2/LD) CY7C42X1V PROGRAMMABLE (PAF) FULL FLAG (FF FULL FLAG (FF Read Enable 2 (REN2) Figure 2. Block Diagram ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ...................................–65 Ambient Temperature with Power Applied............................................. –-55 Supply Voltage to Ground Potential ............... –0.5V to +5.0V DC Voltage Applied to Outputs in ...
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Switching Characteristics Over the Operating Range Parameter Description t Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock HIGH Time CLKH t Clock LOW Time CLKL t Data Set-Up Time DS t Data ...
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Switching Waveforms Write Cycle Timing WCLK D – WEN1 WEN2 (if applicable SKEW1 RCLK REN1,REN2 Read Cycle Timing RCLK t ENS REN1,REN2 EF Q – OLZ OE WCLK WEN1 WEN2 Notes: 11. t ...
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Switching Waveforms (continued) [13] Reset Timing RS REN1, REN2 WEN1 [15] WEN2/LD EF,PAE FF,PAF Notes: 13. The clocks (RCLK, WCLK) can be free-running during reset. 14. After reset, the outputs will be LOW ...
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Switching Waveforms (continued) First Data Word Latency after Reset with Simultaneous Read and Write WCLK –D D (FIRSTVALID WRITE ENS WEN1 WEN2 (if applicable) RCLK EF REN1, REN2 Q – ...
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Switching Waveforms (continued) Empty Flag Timing WCLK –D DATAWRITE1 ENH WEN1 t ENS t t ENS ENH WEN2 (if applicable) t RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q ...
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Switching Waveforms (continued) Full Flag Timing NO WRITE WCLK [11] t SKEW1 D – WEN1 WEN2 (if applicable) RCLK t ENS REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – Programmable Almost Empty Flag ...
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... If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW. 22. PAF offset = m. 23. 64–m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512–m words for CY7C4211V, 1024–m words for CY7C4221V, 2048–m words for CY7C4231V, 4096–m words for CY7C4241V, 8192–m words for CY7C4251V. ...
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... Ordering Information 256 x 9 Low Voltage Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4201V-15AC 25 CY7C4201V-25AC 512 x 9 Low Voltage Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4211V-15AC CY7C4211V-15JC 25 CY7C4211V-25AC CY7C4211V-25JC Low Voltage Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4221V-15AC CY7C4221V-15JC 25 CY7C4221V-25AC Low Voltage Synchronous FIFO ...
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... Document #: 38-06010 Rev. *A © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...
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Document History Page Document Title: CY7C4421V/4201V/4211V/4221V/CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/ Synchronous FIFOs Document Number: 38-06010 REV. ECN NO. Issue Date ** 106471 09/10/01 *A 127857 08/25/03 Document #: 38-06010 Rev. *A CY7C4421V/4201V/4211V/4221V Orig. of Change SZV Change from Spec number: ...