CY7C4225-15AC Cypress Semiconductor Corp, CY7C4225-15AC Datasheet - Page 16

• Manufacturer Part Number: CY7C4225-15AC
• Description: IC SYNC FIFO MEM 1KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4225-15AC

• Function: Synchronous
• Memory Size: 18K (1K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Configuration: Dual
• Density: 18Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 1Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 45mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1217

Depth Expansion Configuration
(with Programmable Flags)
The CY7C42X5 can easily be adapted to applications requir-
ing more than 64/256/512/1024/2048/4096 words of buffering.
Figure 2 shows Depth Expansion using three CY7C42X5s. Maxi-
mum depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First
2. All other devices must have FL in the HIGH state.
DATA IN (D)
Load (FL) control input.
LOAD (LD)
Figure 2. Block Diagram of 192 x 18/768 x 18/1536 x 18/3072 x 18/12288 x 18 Synchronous FIFO Memory
FF
PAF
WRITE ENABLE (WEN)
WRITECLOCK (WCLK)
RESET(RS)
with Programmable Flags used in Depth Expansion Configuration
FIRSTLOAD (FL)
FIRSTLOAD (FL)
FIRSTLOAD (FL)
V
V
CC
CC
FF
PAF
FF
PAF
FF
PAF
WXO RXO
WXO RXO
WXO RXO
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
WXI RXI
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
WXI RXI
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
WXI RXI
16
3. The Write Expansion Out (WXO) pin of each device must be
4. The Read Expansion Out (RXO) pin of each device must be
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion
7. EF, FF, PAE, and PAF are created with composite flags by
PAE
PAE
PAE
EF
EF
EF
tied to the Write Expansion In (WXI) pin of the next device.
tied to the Read Expansion In (RXI) pin of the next device.
Configuration.
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
CY7C4425/4205/4215
CY7C4225/4235/4245
PAE
42X5–23
EF
DATAOUT (Q)