CY7C4235V-15ASC Cypress Semiconductor Corp, CY7C4235V-15ASC Datasheet
CY7C4235V-15ASC
Specifications of CY7C4235V-15ASC
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CY7C4235V-15ASC Summary of contents
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... High-speed, low-power, first-in first-out (FIFO) ■ memories 512 x 18 (CY7C4215V) ❐ (CY7C4225V) ❐ (CY7C4235V) ❐ (CY7C4245V) ❐ 0.65µ CMOS ■ High-speed 67-MHz operation (15-ns read/write cycle times) ■ Low power ■ ...
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... Logic Block Diagram Document #: 38-06029 Rev. *D CY7C4225V/4215V CY7C4235V/4245V Page [+] Feedback [+] Feedback ...
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... Empty Flag .................................................................. 7 Programmable Almost Empty/Almost Full Flag........... 7 Retransmit......................................................................... 7 Width Expansion Configuration...................................... 8 Depth Expansion Configuration (with Programmable Flags) ............................................. 8 Maximum Ratings........................................................... 10 Document #: 38-06029 Rev. *D CY7C4225V/4215V CY7C4235V/4245V Operating Range............................................................. 10 Electrical Characteristics Over the Operating Range ............................................... 10 ...................................................................................... Capacitance Switching Characteristics Over the Operating Range ............................................... 11 Switching Waveforms .................................................... 12 Ordering Information ...
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... Document #: 38-06029 Rev. *D Figure 1. 64-Pin STQFP/TQFP Top View CY7C4215V 41 8 CY7C4225V CY7C4235V 38 11 CY7C4245V CY7C42X5V-15 CY7C42X5V-25 66 CY7C4235V CY7C4245V 64-pin 14x14 TQFP 64-pin 14x14 TQFP 64-pin 10x10 64-pin 10x10 STQFP STQFP CY7C4225V/4215V CY7C4235V/4245V GND GND GND CY7C42X5V-35 Unit 28.6 MHz Page [+] Feedback [+] Feedback ...
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... HIGH, the FIFO’s outputs are in High Z (high-impedance) state. Dual-Mode Pin. Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V synchronized to RCLK, Almost Full synchronized to WCLK.) CY7C4225V/4215V CY7C4235V/4245V /SMODE is tied CC /SMODE is CC /SMODE is tied to V ...
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... LD WEN before ENS 0 0 0–17 outputs 0− outputs even 0− CY7C4225V/4215V CY7C4235V/4245V during a program write will determine the 0–11 Table 2). When the Table 1). Writing all [1] Selection WCLK Writing to offset registers: Empty Offset Full Offset No Operation Write Into FIFO No Operation Page [+] Feedback ...
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... Data written to the FIFO after activation of RT are trans- mitted also. The full depth of the FIFO can be repeatedly retransmitted. HF PAE 7C4245V - [ 2048 2049 to (4096 − 1)) [3] (4096 − 2047 to 4095 4096 CY7C4225V/4215V CY7C4235V/4245V Table 2 FF PAF HF PAE ...
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... PAE and PAF flags are not precise. Document #: 38-06029 Rev. *D RESET (RS) 18 7C4215V 7C4225V 7C4235V 7C4245V FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) CY7C4225V/4215V CY7C4235V/4245V READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE(OE) PROGRAMMABLE(PAF) EMPTYFLAG (EF) EF DATA OUT ( Figure Page [+] Feedback [+] Feedback ...
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... WXO RXO 7C4215V 7C4225V 7C4235V V CC 7C4245V FF EF PAE PAF WXI RXI READ CLOCK (RCLK) WXO RXO READ ENABLE (REN) OUTPUT ENABLE (OE) 7C4215V 7C4225V 7C4235V 7C4245V FF EF PAE PAF WXI RXI CY7C4225V/4215V CY7C4235V/4245V DATAOUT (Q) EF PAE 42X5V–23 Page [+] Feedback [+] Feedback ...
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... Max., Com’ OUT V = Max., Com’ OUT Test Conditions ° MHz 5.0V CC CY7C4225V/4215V CY7C4235V/4245V Ambient Temperature V CC ° ° +70 C 3.3V ± 300 mV 7C42X5V-25 7C42X5V-35 Unit Min Max Min Max 2.4 2.4 V 0.4 0.4 V 2.0 5.0 2.0 5.0 V −0.5 −0.5 ...
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... Document #: 38-06029 Rev 510Ω GND ≤ Vth = 2.0V 7C42X5V-15 Min Max 66 [12 [12] 3 [13] /SMODE tied /SMODE tied [13] /SMODE tied /SMODE tied OHZ . PAF(E) CY7C4225V/4215V CY7C4235V/4245V [9, 10] ALL INPUT PULSES 90% 90% 10% 10% ≤ 7C42X5V-25 7C42X5V-35 Unit Min Max Min Max 40 28.6 MHz ...
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... RCLK and the rising edge of WCLK is less than t Document #: 38-06029 Rev. *D 7C42X5V-15 Min Max 6 Figure 5. Write Cycle Timing t CLK t CLKH CLKL ENH t ENS t WFF , then FF may not change state until the next WCLK edge. SKEW1 CY7C4225V/4215V CY7C4235V/4245V 7C42X5V-25 7C42X5V-35 Unit Min Max Min Max OPERATION t ...
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... Document #: 38-06029 Rev. *D Figure 6. Read Cycle Timing t CLK t CLKH CLKL NO OPERATION t REF t A VALID DATA [15] SKEW2 [16] Figure 7. Reset Timing RSF t RSF t RSF , then EF may not change state until the next RCLK edge. SKEW2 CY7C4225V/4215V CY7C4235V/4245V t REF t OHZ RSR [17 Page [+] Feedback [+] Feedback ...
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... The first word is available the cycle after EF goes HIGH, always. Document #: 38-06029 Rev [18] t FRL t REF OLZ t OE Figure 9. Empty Flag Timing ENS t t REF REF When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4225V/4215V CY7C4235V/4245V [19 ENH [18] t FRL t t REF SKEW2 D0 (maximum) = either 2 FRL CLK SKEW2 CLK Page [+] Feedback [+] Feedback ...
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... Figure 10. Full Flag Timing SKEW1 DATA WRITE t WFF t ENH t A DATAREAD Figure 11. Half-Full Flag Timing t CLKL t t ENS ENH ENS CY7C4225V/4215V CY7C4235V/4245V NO WRITE [14] DATA WRITE t WFF t ENH t ENS t A NEXT DATA READ HALF FULL+1 OR MORE HALF FULL OR LESS t HF Page [+] Feedback [+] Feedback ...
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... If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW. Document #: 38-06029 Rev CLKL t t ENS ENH t PAE t ENS t CLKL t t ENS ENH Note 21 [22] t PAEsynch t ENS CY7C4225V/4215V CY7C4235V/4245V n+1 WORDS n WORDS IN FIFO IN FIFO t PAE WORDS Note 23 INFIFO t PAEsynch t t ENS ENH Page [+] Feedback [+] Feedback ...
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... PAF is offset = m. 26. 256 – m words inCY7C4205V, 512 − m words in CY7C4215V. 1024 – m words in CY7C4225V, 2048 − m words in CY7C4235V, and 4096 – m words in CY7C4245V. 27. 256 − words in CY7C4205V, 512 − words in CY7C4215V, 1024 − CY7C4225V, 2048 − CY74235V, and 4096 − words in CY7C4245V. ...
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... Document #: 38-06029 Rev. *D Figure 16. Write Programmable Registers t CLKL t ENH t DH PAE OFFSET PAF OFFSET Figure 17. Read Programmable Registers t CLKL t ENH t A UNKNOWN PAE OFFSET Figure 18. Write Expansion Out Timing Note CY7C4225V/4215V CY7C4235V/4245V PAE OFFSET D – PAF OFFSET PAE OFFSET Page [+] Feedback [+] Feedback ...
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... For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06029 Rev. *D Figure 19. Read Expansion Out Timing Note Figure 20. Write Expansion In Timing XIS Figure 21. Read Expansion In Timing [33, 34, 35] Figure 22. Retransmit Timing t PRT RTR CY7C4225V/4215V CY7C4235V/4245V XIS t RTR . RTR to update these flags. Page [+] Feedback [+] Feedback ...
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... Ordering Information Speed Ordering Code (ns) 512 x 18 Low-Voltage Synchronous FIFO 15 CY7C4215V-15ASXC Low-Voltage Synchronous FIFO 15 CY7C4225V-15ASXC Low-Voltage Synchronous FIFO 15 CY7C4235V-15ASC CY7C4235V-15ASXC Low-Voltage Synchronous FIFO 15 CY7C4245V-15ASXC 25 CY7C4245V-25ASC Document #: 38-06029 Rev. *D Package Package Name Type A64 64-Pin Pb-Free 10x10 Thin Quad Flatpack A64 64-Pin Pb-Free 10x10 Thin Quad Flatpack ...
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... Package Diagrams Document #: 38-06029 Rev. *D Figure 23. 64-Pin TQFP (10X10X1.4 mm) CY7C4225V/4215V CY7C4235V/4245V 51-85051 *B Page [+] Feedback [+] Feedback ...
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... Document #: 38-06029 Rev. *D Figure 24. 64-Pin TQFP (14X14X1.4 mm) CY7C4225V/4215V CY7C4235V/4245V 51-85046 *D Page [+] Feedback [+] Feedback ...
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... Document History Page Document Title: CY7C4225V/4215V/CY7C4235V/4245V 64/256/512/1K/2K/ Low-Voltage Synchronous FIFOs Document Number: 38-06029 Submission REV. ECN NO. Date ** 109961 12/17/01 *A 122281 12/26/02 *B 127856 08/22/03 *C 393636 See ECN *D 2896039 03/19/2010 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office ...