NJU26102FR1 New Japan Radio Co., Ltd., NJU26102FR1 Datasheet - Page 4

• Manufacturer Part Number: NJU26102FR1
• Description: DSP, Digital Signal Processor for TV
• Manufacturer: New Japan Radio Co., Ltd.

NJU26102
■ Audio Interface
The NJU26102 audio interface provides industry serial data formats of I
Right-justified. The NJU26102 audio interface provides three data inputs, SDI0, SDI1, and SDI2, and three data
outputs, SDO0, SDO1, and SDO3, as shown in table 2 and 3. The input serial data is selected by the firmware
command.
■ Host Interface
The NJU26102 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : 4-Wire
serial bus or I
in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and
initiates data transfers, regardless of the chosen communication protocol.
The detail 4-Wire Serial bus and I
Sheet”.
■ I
AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. These pins offer
additional flexibility to SLAVE address. 4 addresses could be chosen by AD1 and AD2-pin. The AD1 and AD2-pin
addresses are decided by the connections of AD1 and AD2-pin. The AD1 and AD2 addresses should be the same
level as AD1 and AD2-pin connections.
* AD1 or AD2 address is 0 when AD1 or AD2-pin is “L”. AD1 or AD2 address is 1 when AD1 or AD2-pin is “H”.
The detail I
- 4 -
2
C address
2
C bus timing of the NJU26102 is described in the “ NJU26100 Series Hardware Data Sheet”.
2
C bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only
bit7
0
Table 4 I
Table 2
Table 3
Pin No.
Pin No.
25
26
27
3
2
1
bit6
0
2
C Bus SLAVE Address
Serial Audio Input Pin
Serial Audio Output Pin
2
Symbol
Symbol
C bus information are described in the “ NJU26100 Series Hardware Data
SDO0
SDO1
SDO2
SDI0
SDI1
SDI2
bit5
1
bit4
1
Audio Data Output 0 L / R
Audio Data Output 1 L / R
Audio Data Output 2 L / R
Audio Data Input 0 L / R
Audio Data Input 1 L / R
Audio Data Input 2 L / R
bit3
1
Description
Description
bit2
AD2
*
2
S, MSB-first left-justified or MSB-first
bit1
AD1
*
bit0
R/W
Ver.2004-08-26