CY7C4211-10AXI Cypress Semiconductor Corp, CY7C4211-10AXI Datasheet - Page 10
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CY7C4211-10AXI
Manufacturer Part Number
CY7C4211-10AXI
Description
IC SYNC FIFO MEM 512X9 32-TQFP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Specifications of CY7C4211-10AXI
Function
Synchronous
Memory Size
4.6K (512 x 9)
Data Rate
100MHz
Access Time
8ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TQFP
Configuration
Dual
Density
4Kb
Access Time (max)
8ns
Word Size
9b
Organization
512x9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
40mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4211-10AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C4211-10AXIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-06016 Rev. *B
Switching Waveforms
Notes:
First Data Word Latency after Reset with Simultaneous Read and Write
Empty Flag Timing
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
19. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
20. When t
21. The first word is available the cycle after EF goes HIGH, always.
(if applicable)
WEN2
Q
for the programmable flag offset registers.
t
D
CLK
WEN1
REN1,
WCLK
REN2
0
RCLK
0
–Q
–D
OE
+ t
EF
SKEW1
8
SKEW1
8
(if applicable)
D
LOW
Q
WEN2
WCLK
WEN1
REN1,
t
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
RCLK
> minimum specification, t
REN2
DS
0
0
–D
–Q
OE
EF
t
t
ENS
ENS
8
8
DATAWRITE1
t
ENS
t
DS
(continued)
t
SKEW1
DATA IN OUTPUT REGISTER
t
ENH
t
ENH
D
0 (FIRST
t
FRL
FRL
(maximum) = t
[20]
VALID
t
SKEW1
Write)
t
OLZ
t
FRL
t
REF
CLK
[20]
+ t
SKEW1
t
D
REF
1
. When t
t
OE
t
SKEW1
A
t
REF
< minimum specification, t
t
DS
t
A
D
[21]
2
t
t
ENS
ENS
CY7C4421/4201/4211/4221
DATAWRITE2
t
ENH
t
SKEW1
t
ENH
CY7C4231/4241/4251
D
0
FRL
D
t
A
t
3
FRL
(maximum) = either 2*t
DATA Read
[20]
D
1
D
t
4
REF
Page 10 of 18
CLK
+ t
SKEW1
or