ST62T45B STMicroelectronics, ST62T45B Datasheet - Page 42

• Manufacturer Part Number: ST62T45B
• Description: 8-BIT OTP/EPROM MCU
• Manufacturer: STMicroelectronics

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41
ST62T45B/E45B
TIMER 1& 2 (Cont’d)
4.2.5 TIMER 1 Registers
Timer Status Control Register (TSCR)
Address: 0D4h — Read/Write
Bit 7 = TMZ: Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit
must be cleared by user software before starting a
new count.
Bit 6 = ETI: Enable Timer Interrup
When set, enables the timer interrupt request. If
ETI=0 the timer interrupt is disabled. If ETI=1 and
TMZ=1 an interrupt request is generated.
Bit 5 = TOUT: Timer Output Control.
When low, this bit select the input mode for the
TIMER pin. when high the output mode is select-
ed.
Bit 4 = DOUT: Data Ouput
Data sent to the timer output when TMZ is set high
(output mode only). Input mode selection (input
mode only)
Bit 3 = PSI : Prescaler Initialize Bit
Used to initialize the prescaler and inhibit its
counting. When PSI=“0” the prescaler is set to
7Fh and the counter is inhibited. When PSI=“1”
the prescaler is enabled to count downwards. As
long as PSI=“0” both counter and prescaler are
not running.
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TMZ
7
ETI
TOUT DOUT
PSI
PS2
PS1
PS0
0
Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
lect. These bits select the division ratio of the pres-
caler register.
Table 15. Prescaler Division Factors
Timer Counter Register (TCR)
Address: 0D3h —
Bit 7-0 = D7-D0 : Counter Bits.
Prescaler Register PSC
Address: 0D2h —
Bit 7 = D7: Always read as ”0”.
Bit 6-0 = D6-D0: Prescaler Bits.
D7
D7
7
7
PS2
0
0
0
0
1
1
1
1
D6
D6
D5
D5
PS1
1
0
0
1
1
0
0
1
D4
D4
Read/Write
Read/Write
D3
D3
PS0
1
0
1
0
1
0
1
0
D2
D2
Divided by
D1
D1
128
16
32
64
8
1
2
4
D0
D0
0
0