AD9517-1 Analog Devices, Inc., AD9517-1 Datasheet - Page 47

• Manufacturer Part Number: AD9517-1
• Description: 12-output Clock Generator With Integrated 2.5 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Case 1
When Φ
Δ
Case 2
When Φ
Δ
Case 3
When Φ
Δ
Case 4
When Φ
Δ
(Φ
Fine Delay Adjust (Divider 2 and Divider 3)
Each AD9517 LVDS/CMOS output (OUT4 to OUT7) includes
an analog delay element that can be programmed to give
variable time delays (Δ
The amount of delay applied to the clock signal is determined
by programming four registers per output (see Table 46).
Table 46. Setting Analog Fine Delays
OUTPUT
(LVDS/CMOS)
OUT4
OUT5
OUT6
OUT7
CLK
t
t
t
t
= Φ
= Φ
= (Φ
=
X.1
DIVIDER
− 16 + M
VCO
x.1
X.1
X.1
DIVIDER
x.1
x.1
X.1
X.1
× T
× T
− 16 + M
X.1
≤ 15 and Φ
≤ 15 and Φ
≥ 16 and Φ
≥ 16 and Φ
X.1
X.1
X.1
+ Φ
+ (Φ
Figure 54. Fine Delay (OUT4 to OUT7)
Ramp
Capacitors
0xA1<5:3>
0xA4<5:3>
0xA7<5:3>
0xAA<5:3>
+ 1) × T
X.2
DIVIDER
X.1
X.2
X.2
× T
+ 1) × T
x.2
x.2
X.2
X.2
− 16 + M
t
) in the clock signal at that output.
≤ 15:
≥ 16:
x.2
≤ 15:
≥ 16:
X.1
+ (Φ
FINE DELAY
FINE DELAY
X.1
Ramp
Current
0xA1<2:0>
0xA4<2:0>
0xA7<2:0>
0xAA<2:0>
BYPASS
ADJUST
BYPASS
ADJUST
X.2
+ Φ
X.2
ΔT
ΔT
+ 1) × T
− 16 + M
X.2
× T
CMOS
CMOS
CMOS
CMOS
LVDS
LVDS
X.2
X.2
Delay
Fraction
0xA2<5:0>
0xA5<5:0>
0xA8<5:0>
0xAB<5:0>
X.2
+ 1) × T
OUTPUT
DRIVERS
X.2
OUTM
OUTM
OUTN
OUTN
Delay
Bypass
0xA0<0>
0xA3<0>
0xA6<0>
0xA9<0>
Rev. 0 | Page 47 of 80
Calculating the Fine Delay
The following values and equations are used to calculate the
delay of the delay block:
I
Number of Capacitors = Number of Bits = 0 in Ramp Capacitors + 1
Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3;
001 = 2 + 1 = 3; 111 = 0 + 1 = 1.
Delay Range (ns) = 200 × ((No. of Caps + 3)/(I
Delay Full Scale (ns) = Delay Range + Offset
Fine Delay (ns) = Delay Range × Delay Fraction × (1/63) + Offset
Note that only delay fraction values up to 47 decimals (101111b;
0x2F) are supported.
In no case can the fine delay exceed one-half of the output clock
period. If a delay longer than half of the clock period is attempted,
the output stops clocking.
The delay function adds some jitter greater than that specified
for the nondelayed output. This means that the delay function
should be used primarily for clocking digital chips, such as
FPGA, ASIC, DUC, and DDC. An output with this delay
enabled may not be suitable for clocking data converters. The
jitter is higher for long full scales because the delay block uses a
ramp and trip points to create the variable delay. A slower ramp
time produces more time jitter.
Synchronizing the Outputs—SYNC Function
The AD9517 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions and subsequently releasing these
outputs to continue clocking at the same instant with the preset
conditions applied. This allows for the alignment of the edges of
two or more outputs or for the spacing of edges according to the
coarse phase offset settings for two or more outputs.
Offset
RAMP
(μA) = 200 × (Ramp Current + 1)
( )
ns
=
0.34
+
(
1600
−
I
RAMP
)
×
10
−
4
+
⎛
⎜
⎜
⎝
RAMP
No.
of
)) × 1.3286
I
AD9517-1
RAMP
Caps
−
1
⎞
× ⎟ ⎟
⎠
6