AD9518-1 Analog Devices, Inc., AD9518-1 Datasheet - Page 2

• Manufacturer Part Number: AD9518-1
• Description: 6-output Clock Generator With Integrated 2.5 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9518-1
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Diagrams............................................................................ 12
Absolute Maximum Ratings.......................................................... 13
Pin Configuration and Function Descriptions........................... 14
Typical Performance Characteristics ........................................... 16
Terminology .................................................................................... 20
Detailed Block Diagram ................................................................ 21
Theory of Operation ...................................................................... 22
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 6
Clock Outputs ............................................................................... 6
Timing Characteristics ................................................................ 7
Clock Output Additive Phase Noise (Distribution Only; VCO
Divider Not Used) ........................................................................ 7
Clock Output Absolute Phase Noise (Internal VCO Used).... 8
Clock Output Absolute Time Jitter (Clock Generation Using
Internal VCO) ............................................................................... 8
Clock Output Absolute Time Jitter (Clock Cleanup Using
Internal VCO) ............................................................................... 9
Clock Output Absolute Time Jitter (Clock Generation Using
External VCXO) ........................................................................... 9
Clock Output Additive Time Jitter (VCO Divider
Not Used)....................................................................................... 9
Clock Output Additive Time Jitter (VCO Divider Used) ....... 9
Serial Control Port ..................................................................... 10
PD , SYNC , and RESET Pins ..................................................... 10
LD, STATUS, and REFMON Pins............................................ 11
Power Dissipation....................................................................... 11
Thermal Resistance .................................................................... 13
ESD Caution................................................................................ 13
Operational Configurations...................................................... 22
High Frequency Clock Distribution—CLK or External
VCO >1600 MHz ................................................................... 22
Internal VCO and Clock Distribution................................. 24
Clock Distribution or External VCO <1600 MHz............. 25
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Serial Control Port ......................................................................... 41
Digital Lock Detect (DLD) ....................................................... 31
Clock Distribution ..................................................................... 35
Reset Modes ................................................................................ 39
Power-Down Modes .................................................................. 40
Serial Control Port Pin Descriptions....................................... 41
Phase-Locked Loop (PLL) .................................................... 27
Configuration of the PLL ...................................................... 27
Phase Frequency Detector (PFD) ........................................ 27
Charge Pump (CP)................................................................. 28
On-Chip VCO ........................................................................ 28
PLL External Loop Filter....................................................... 28
PLL Reference Inputs............................................................. 28
Reference Switchover............................................................. 29
Reference Divider R............................................................... 29
VCXO/VCO Feedback Divider N: P, A, B, R ..................... 29
Analog Lock Detect (ALD)................................................... 31
Current Source Digital Lock Detect (DLD) ....................... 31
External VCXO/VCO Clock Input (CLK/ CLK ) ................ 31
Holdover.................................................................................. 32
Manual Holdover Mode ........................................................ 32
Automatic/Internal Holdover Mode.................................... 32
Frequency Status Monitors ................................................... 33
VCO Calibration .................................................................... 34
Internal VCO or External CLK as Clock Source ............... 35
CLK or VCO Direct to LVPECL Outputs........................... 35
Clock Frequency Division..................................................... 36
VCO Divider........................................................................... 36
Channel Dividers—LVPECL Outputs................................. 36
Synchronizing the Outputs—SYNC Function ................... 37
LVPECL Clock Outputs: OUT0 to OUT5 .......................... 39
Power-On Reset—Start-Up Conditions when V
Is Applied ................................................................................ 39
Asynchronous Reset via the RESET Pin ............................. 40
Soft Reset via 0x00<5> .......................................................... 40
Chip Power-Down via PD .................................................... 40
PLL Power-Down................................................................... 40
Distribution Power-Down .................................................... 40
Individual Clock Output Power-Down............................... 40
Individual Circuit Block Power-Down................................ 40
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