AD9887A Analog Devices, Inc., AD9887A Datasheet - Page 17

• Manufacturer Part Number: AD9887A
• Description: Dual Interface For Flat Panel Displays
• Manufacturer: Analog Devices, Inc.

THEORY OF OPERATION AND DESIGN GUIDE—ANALOG INTERFACE
GENERAL DESCRIPTION
The AD9887A is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel monitors
or projectors. The device is ideal for implementing a computer
interface in HDTV monitors or for serving as the front end to
high performance video scan converters.
Implemented in a high performance CMOS process, the interface
can capture signals with pixel rates of up to 170 MHz, or of up
to 340 MHz with an alternate pixel sampling mode.
The AD9887A includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a 2-wire
serial interface. Full integration of these sensitive analog functions
makes system design straightforward and less sensitive to the
physical and electrical environment.
With an operating temperature range of 0°C to 70°C, the device
requires no special environmental considerations.
INPUT SIGNAL HANDLING
The AD9887A has three high impedance analog input pins for
the red, green, and blue channels that accommodate signals
ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a DVI-I
connector, a 15-lead D connector, or BNC connectors. The
AD9887A should be located as close as is practical to the input
connector. Signals should be routed via matched-impedance
traces (normally 75 Ω) to the IC input pins.
At this point, the signal should be resistively terminated (75 Ω
to the signal ground return) and capacitively coupled to the
AD9887A inputs through 47 nF capacitors. These capacitors
form part of the dc-restoration circuit (see Figure 3).
In an ideal world of perfectly matched impedances, the best
performance would be obtained with the widest possible signal
bandwidth. The wide bandwidth inputs of the AD9887A
(330 MHz) would track the input signal continuously as it moves
from one pixel level to the next and would digitize the pixel during
a long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise that result in excessive ringing
and distortion of the input waveform. This makes it difficult to
establish a sampling phase that provides good image quality.
A small inductor in series with the input can be effective in rolling
off the input bandwidth slightly and providing a high quality signal
over a wider range of conditions. Using a Fair-Rite #2508051217Z0
high speed signal chip bead inductor in the circuit of Figure 3
provides good results in most applications.
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HSYNC AND VSYNC INPUTS
The AD9887A receives a horizontal sync signal and uses it to
generate the pixel clock and clamp timing. It is possible to
operate the AD9887A without applying Hsync (using an
external clock), but several of the chip’s features are unavailable.
Therefore, it is recommended to provide Hsync. It can be in the
form of either a sync signal directly from the graphics source or
a preprocessed TTL- or CMOS-level signal.
The HSYNC input includes a Schmitt-trigger buffer and is capable
of handling signals that have long rise times with superior noise
immunity. In typical PC-based graphics systems, the sync signals
are simply TTL-level drivers feeding unshielded wires in the
monitor cable. As such, no termination is required or desired.
When the VSYNC input is selected as the source for Vsync, it is
used for coast generation and passed through to the VSOUT pin.
Serial Control Port
The serial control ports are designed for 3.3 V logic. If there are
5 V drivers on the bus, the serial control port pins should be
protected with 150 Ω series resistors placed between the pull-up
resistors and the input pins.
Output Signal Handling
The digital outputs are designed and specified to operate from a
3.3 V power supply (V
2.5 V for compatibility with 2.5 V logic.
CLAMPING
RGB Clamping
To digitize the incoming signal properly, adjust the dc offset of
the input to fit the range of the on-board ADCs.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground, the black level is at 300 mV, and the white level is at
approximately 1.0 V. Some common RGB line amplifier boxes
use emitter-follower buffers to split signals and increase drive
capability. This introduces a 700 mV dc offset to the signal.
Clamping removes this offset to allow proper capture.
INPUT
RGB
Figure 3. Analog Input Interface Circuit
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AD9887A
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