AD9520 Analog Devices, Inc., AD9520 Datasheet - Page 52

• Manufacturer Part Number: AD9520
• Description: 12 Lvpecl/24 Cmos Output Clock Generator
• Manufacturer: Analog Devices, Inc.

AD9520-5
Table 41. Serial Control Port Timing
Parameter
t
t
t
t
t
t
t
t
DS
DH
CLK
S
C
HIGH
LOW
DV
SCLK
SDIO
CS
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between the CS falling edge and SCLK rising edge (start of communication cycle)
Setup time between SCLK rising edge and the CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 54)
t
DS
t
S
BIT N
t
HIGH
t
DH
Figure 56. Serial Control Port Timing—Write
t
CLK
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t
LOW
BIT N + 1
t
C