AD9522-5 Analog Devices, Inc., AD9522-5 Datasheet
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AD9522-5
Manufacturer Part Number
AD9522-5
Description
12 Lvds/24 Cmos Output Clock Generator
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9522-5.pdf
(76 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9522-5BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
FEATURES
Low phase noise, phase-locked loop (PLL)
Twelve 800 MHz LVDS outputs divided into 4 groups
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9522-5
with subpicosecond jitter performance, along with an on-chip PLL
that can be used with an external VCO.
1
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-5 is used, it is referring to that specific
member of the AD9522 family.
Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVPECL, or LVDS references to 250 MHz
Accepts 16.62 MHz to 33.33 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Auto and manual reference switchover/holdover modes
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Each group of 3 has a 1-to-32 divider with phase delay
Additive broadband jitter as low as 242 fs rms
Channel-to-channel skew grouped outputs < 60 ps
Each LVDS output can be configured as 2 CMOS outputs
and other 10 Gbps protocols
with selectable revertive/nonrevertive switching
(for f
OUT
≤ 250 MHz)
1
provides a multioutput clock distribution function
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
The AD9522 serial interface supports both SPI and I2C® ports.
An in-package EEPROM can be programmed through the
serial interface and store user-defined register settings for
power-up and chip reset.
The AD9522 features 12 LVDS outputs in four groups. Any of
the 800 MHz LVDS outputs can be reconfigured as two
250 MHz CMOS outputs.
Each group of outputs has a divider that allows both the divide
ratio (from 1 to 32) and the phase (coarse delay) to be set.
The AD9522 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. The external VCO can have an
operating voltage up to 5.5 V.
The AD9522 is specified for operation over the standard industrial
range of −40°C to +85°C.
The
LVPECL/CMOS drivers instead of LVDS/CMOS drivers.
REFIN
REFIN
CLK
AD9520-5
12 LVDS/24 CMOS Output
FUNCTIONAL BLOCK DIAGRAM
SPI/I
DIGITAL LOGIC
REF1
REF2
PORT AND
is an equivalent part to the AD9522-5 featuring
2
C CONTROL
AND MUXES
©2008 Analog Devices, Inc. All rights reserved.
DIVIDER
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
CP
EEPROM
Figure 1.
Clock Generator
LVDS/
CMOS
AD9522-5
MONITOR
AD9522-5
STATUS
DELAY
ZERO
www.analog.com
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11