TS68040MR25A Atmel Corporation, TS68040MR25A Datasheet - Page 23
TS68040MR25A
Manufacturer Part Number
TS68040MR25A
Description
Manufacturer
Atmel Corporation
Datasheet
1.TS68040MR25A.pdf
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Table 16. JTAG Timing Application (Figure 16 to Figure 19)
-55°C T
2116A–HIREL–09/02
Num
10
11
12
13
1
2
3
4
5
6
7
8
9
C
T
J
max; 4.75V V
Characteristic
TCK Frequency
TCK Cycle Time
TCK Clock Pulse Width Measured at 1.5V
TCK Rise and Fall Times
TRST Setup Time to TCK Falling Edge
TRST Assert Time
Boundary Scan Input Data Setup Time
Boundary Scan Input Data Hold Time
TCK to Output Data Valid
TCK to Output High Impedance
TMS, TDI Data Setup Time
TMS, TDI Data Hold Time
TCK to TDO Data Valid
TCK to TDO High Impedance
CC
5.25V unless otherwise specified
Figure 9. Read/Write Timing
Note:
Transfer attribute signals UPAN, SIZN, TTN, TMN, TLNN, R/W, LOCK, LOCKE, CIOUT
(1)(2)
Min
100
100
40
40
50
50
20
5
0
0
0
0
0
0
Max
TS68040
10
10
50
50
20
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23
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