TS68302MAB Atmel Corporation, TS68302MAB Datasheet
TS68302MAB
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TS68302MAB Summary of contents
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Features • TS68000/TS68008 Microprocessor Core Supporting a 16- or 8-bit TS68000 Family • System Integration Block Including: – Independent Direct Memory Access (IDMA) Controller – Interrupt Controller with Two Modes of Operation – Parallel Input/output (I/O) Ports, some with Interrupt ...
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Screening/Quality This product is manufactured in full compliance with either: • MIL-STD-883 (class B) • DESC. Drawing 5962-93159 • Or according to Atmel standards R suffix PGA 132 (Ceramic Pin Grid Array) Introduction TS68302 2 The TS68302 integrated multiprotocol processor ...
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Figure 1. TS68302 Block Diagram TS68000 BUS INTERRUPT CONTROLLER IDMA (1 CHANNEL) DRAM REFRESH CONTROLLER (6 CHANNELS) MAIN CONTROLLER (RISC) 2117A–HIREL–11/02 TS68000/TS68008 CORE ON-CHIP PERIPHERALS BUS INTERFACE UNIT 1152 BYTES DUAL-PORT BUS ARBITER STATIC RAM TIMERS (3) PARALLEL I/O PERIPHERAL ...
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Pin Assignments TS68302 4 Figure 2. PGA Terminal Designation N PB10 TIN1 IACK1 GND UDS M CS3 TOUT2 TIN2 VDD IACK7 L CS2 PB11 GND TOUT1 IACK6 LDS K RMC IAC PB9 WDOG CS0 J FC2 PB8 CS1 H VDD ...
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Figure 4. Functional Signal Groups NMSI1/ISDN I/F RXD1/L1RXD TXD1/L1TXD RCLK1/L1CLK TCLK1/L1SY0/SDS1 CD1/L1SY1 CTS1/L1RG RTS1/L1RQ/GCIDCL BRG1 NMSI2/PIO RXD2/PA0 TXD2/PA1 RCLK2/PA2 TCLK2/PA3 CTS2/PA4 RTS2/PA5 CD2/PA6 BRG2/SDS2/PA7 NMSI3/SCP/PIO RXD3/PA8 TXD3/PA9 RCLK3/PA10 TCLK3/PA11 CTS3/SPRXD RTS3/SPTXD CD3/SPCLK BRG3/PA12 IDMA/PAIO DREQ/PA13 DACK/PA14 DONE/PA15 IACK/PBIO IACK7/PB0 ...
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Signal Descriptions Table 1. Signal Definitions Functional Group Signals Clocks XTAL, EXTAL, CLKO System Control RESET, HALT, BERR, BUSW, DISCPU Address Bus A23-A1 Data Bus D15-D0 Bus Control AS, R/W, UDS/A0, LDS/DS, DTACK Bus Control RMC, IAC, BCLR Bus Arbitration ...
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Design and Construction Terminal Connections Lead Material and Finish Package Electrical Characteristics Table 2. Absolute Maximum Ratings Symbol Parameter P Power Dissipation (typical at 16.67 MHz Power Dissipation (typical at 8 MHz Low Power Mode Dissipation ...
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Figure 5. Clock Input Timing Diagram 2.0V 0. (C) Note: Timing measurements are referenced to and from a low voltage of 0.8V and a voltage of 2.0V, unless otherwise noted. The volt- age swing through this range should ...
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Mechanical and Environment Marking Quality Conformance Inspection DESC/MIL-STD-883 Electrical Characteristics General Requirements 2117A–HIREL–11/02 The total thermal resistance of a package ( θ θ and θ , representing the barrier to heat flow from the semiconductor junction to the JC CA ...
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Table 5. DC Electrical Characteristics V = 5.0 V ± 10%; GND = Symbol Parameter V Input High Voltage (except EXTAL Input Low Voltage (except EXTAL Input High Voltage (EXTAL) CIH ...
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Table 6. DC Electrical Characteristics - NMSI1 in IDL mode Symbol Parameter V Power DD V Common SS T Temperature Input Pin Characteristics: L1CLK, L1SY1, L1R x D, L1GR V Input Low Level Voltage IL V Input High Level Voltage ...
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Dynamic (Switching) Characteristics Figure 6. Clock Timing Diagram V CIH = 4V EXTAL V CIL = 0.6V CLKO Table 7. AC Electrical Specifications - Clock Timing (see Figure 7) Num. Symbol Parameter f Frequency of Operation 1 t Clock Period ...
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Table 8. AC Electrical Specifications IMP Bus Master Cycles (see Figure 7, Figure 8 and Figure 16.67 MHz Num. Symbol Parameter 6 t Clock high to FC, address valid CHFCADV 7 t Clock high to address, data ...
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Table 8. AC Electrical Specifications IMP Bus Master Cycles (see Figure 7, Figure 8 and Figure 16.67 MHz (Continued) Num. Symbol Parameter 44 t AS, DS negated to AVEC negated SHVPH 46 t BGACK width low GAL ...
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Figure 7. Read Cycle Timing Diagram CLKO FC2-FC0 A23- LDS-UDS R/W DTACK DATA IN BERR/BR (Note 2) HALT / RESET ASYNCHRONOUS INPUTS (Note 1) Notes: 1. Setup time for asynchronous inputs IPL2-IPL0 guarantees their recognition at the next ...
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Figure 8. Write Cycle Timing Diagram OUT Notes: 1. Timing measurements are referenced to and from a low voltage of 0.8V and a high of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass ...
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Figure 9. Bus Arbitration Timing Diagram STROBES AND R/W BR BGACK CLKO Note: Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, and IPL2-IPL0 guarantees their recog- nition at the next falling ...
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Figure 10. DMA Timing Diagram Table 10. AC Electrical Specifications - External Master Internal Asynchronous Read/write Cycles Num. Symbol Parameter 100 t R/W valid to DS low RWVDSL 101 t DS low to data in valid DSLDIV 102 t DTACK ...
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Figure 11. External Master Internal Asynchronous Read Cycle Timing Diagram 2117A–HIREL–11/02 TS68302 19 ...
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Figure 12. External Master Internal Asynchronous Write Cycle Timing Diagram Table 11. AC Electrical Specifications External Master Internal Synchronous Read/write Cycles Num. Symbol Parameter 110 t Address valid to AS low AVASL 111 t AS low to clock high ASLCH ...
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Table 11. AC Electrical Specifications External Master Internal Synchronous Read/write Cycles Num. Symbol Parameter 123 t AS high to DTACK high ASHDTH 124 t DTACK high to DTACK high impedance DTHDTZ 125 t Clock high to data out valid CHDOV ...
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Figure 14. External Master Internal Synchronous Read Cycle Timing Diagram (One Wait State) TS68302 22 2117A–HIREL–11/02 ...
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Figure 15. External Master Internal Synchronous Write Cycle Timing Diagram Table 12. AC Electrical Specifications - Internal Master Read/write Cycles Num. Symbol Parameter 140 t Clock high to IAC high CHIAH 141 t Clock low to IAC low CLIAL 142 ...
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Figure 16. Internal Master Internal Read Cycle Timing Diagram CLKO (OUTPUT) A23-A1 (OUTPUT) AS (OUTPUT) IAC (OUTPUT) UDS LDS (OUTPUT) R/W (OUTPUT) D15-D0 (OUTPUT) DTACK (OUTPUT) Table 13. AC Electrical Specifications - Chip-select Timing Internal Master Num. Symbol Parameter 150 ...
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Table 13. AC Electrical Specifications - Chip-select Timing Internal Master Num. Symbol Parameter 176 t CS negated to R/W invalid CSNRWI 177 t CS asserted to R/W low (write) CSARWL 178 t CS negated to data in invalid (hold time ...
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Table 15. AC Electrical Specifications - Parallel I/O Num. Symbol Parameter 180 t Input Data Setup Time (to clock low) DSU 181 t Input Data Hold Time (from clock low) DH Clock High to Data Out Valid (CPU writes data, ...
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Table 16. AC Electrical Specifications - Interrupts Num. Symbol Parameter 190 t Interrupt pulse width low IRQ (edge triggered mode) IPW 191 t Minimum time between active edges AEMT Note: 1. Set up time for the asynchronous inputs IPL2-IPL0 and ...
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Table 18. AC Electrical Specifications - Serial Communication Port Num. Parameter 250 SPCLK clock output period 251 SPCLK clock output rise/fall time 252 Delay from SPCLK to transmit (1) 253 SCP receive setup time (1) 254 SPC receive hold time ...
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Table 19. AC Electrical Specifications - Idle Timing are referenced to the L1CLK at 50% point of VDD (Continued) Num. Parameter 274 L1GR hold time (from L1SY1 falling edge) 275 SDS1-SDS2 active delay from L1CLK rising edge 276 SDS1-SDS2 inactive ...
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Table 20. AC Electrical Specifications - GCI Timing GCI supports the NORMAL mode and the GCI channel 0 (GCN0) in MUX mode. Normal mode uses 512 kHz clock rate (256K bit rate). MUX mode uses 256 3068K ...
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Figure 24. GSI Timing Diagram Table 21. AC Electrical Specifications - PCM Timing There are two sync types: Short frame - Sync signals are one clock cycle prior to the data. Long frame - Sync signals are N-bits that envelope ...
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Table 22. AC Electrical Specifications - NMSI Timing The NMSI mode uses two clocks, one for receive and one for transmit. Both clocks can be internal or external. When the clock is internal generated by the internal baud ...
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Figure 26. NMSI Timing Diagram 317 RCLK1 321 RXD1 (INPUT) CD1 (INPUT) CD1 (SYNC INPUT) 317 TCLK1 TXD1 (OUTPUT) RTS1 (OUTPUT) CTS1 (INPUT) 2117A–HIREL–11/02 316 317 315 322 316 317 315 318 319 TS68302 323 322 319 320 33 ...
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Functional Description Figure 27. Buffer Memory Structure DUAL-PORT RAM (1152 BYTES) TX DATA BUFFER SCC1 BUFFER DESCRIPTORS TABLE SCC2 BUFFER DESCRIPTORS TABLE SCC3 BUFFER DESCRIPTORS TABLE SCP DESCRIPTOR SMC1 DESCRIPTOR SMC2 DESCRIPTOR TS68302 34 The TS68302 uses a microprocessor architecture ...
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Core Overview System Integration Block (SIB) IDMA Controller Interrupt Controller 2117A–HIREL–11/02 The TS68302 allows operation either in the full 68000 mode with a 16-bit data bus or in the 68008 mode with an 8-bit data bus. The TS68302 has ...
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Figure 28. Interrupt Controller Block Diagram 3 TIMERS 1 SCP 2 SMCs 2 DMA 4 PB8-PB11 SCC1 EVENT REGISTER SCC1 MASK REGISTER SCC2 EVENT REGISTER SCC2 MASK REGISTER SCC3 EVENT REGISTER SCC3 MASK REGISTER Parallel I/O Ports TS68302 36 1 ...
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Dual-Port RAM Timers External Chip-select Signals and Wait-state Logic Clock Generator 2117A–HIREL–11/02 The IMP has 1152 bytes of RAM configured as a dual-port memory. The RAM can be accessed by the internal RISC controller or one of three bus masters: ...
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System Control System Control Register Disable CPU Logic (68000) Freeze Control DRAM Refresh Controller Communications Processor TS68302 38 The IMP system control consists of a system control register (SCR) containing bits for the following system control functions: • system status ...
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Main Controller Serial Communication Controllers 2117A–HIREL–11/02 The main controller is a microcode RISC processor that services all the serial channels. The main controller transfers data between the serial channels and internal/external RAM, executes host commands, and generates interrupts to the ...
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TS68302 40 • detection of frames that are too long, • programmable FLAGS between successive frames, • automatic retransmission in case of collision. The SCC BISYNC mode key features are as follows: • flexible data buffers, • ...
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Serial Communication Port Serial Management Controllers Serial Channels Physical Interface 2117A–HIREL–11/02 • maintenance of four 16-bit error counters, • provides asynchronous link over which DDCMP may be used, • Flow control character transmission supported. The SCP is a full-duplex, synchronous, ...
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Figure 29. Serial Channels Physical Interface Block Diagram MASK REGISTER TO SMC1 PHYSICAL INTERFACE BUS LAYER-1 BUS INTERFACE ISDN INTERFACE OR SCC1 TS68302 42 TS68000 DATA BUS SIMASK TO SMC2 TIME-SLOT ASSIGNER SIMODE MODE REGISTER TO SCC1 TO SCC2 TO ...
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Preparation For Delivery Packaging Certificate of Compliance Handling 2117A–HIREL–11/02 Microcircuits are prepared for delivery in accordance with MIL-STD-1835. Atmel offers a certificate of compliance with each shipment of parts, affirming the prod- ucts are in compliance either with MIL-STD-883 or ...
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Package Mechanical Data 132-pin - Ceramic Pin Grid Array (in millimeter) TOP VIEW 34.544 ± 0.254 TS68302 44 2.54 BSC 4.57 ± 0.025 1.27 ± 0.025 1.27 ...
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... Terminal Connections 132-pin - Ceramic Pin Grid Array 132-pin - Ceramic Quad Flat Pack/CERQUAD Ordering Information HI-REL Product Commercial Atmel Part-Number TS68302MRB/C16 MIL-STD-883 TS68302MAB/C16 MIL-STD-883 TS68302DESC01QXC TS68302DESC01QYA Note: 1. Gullwing leads. 2117A–HIREL–11/ Top view See Figure 2. See Figure 3. Norms ...
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Standard Product Commercial Atmel Part-Number TS68302VR16 Atmel Standard TS68302MR16 Atmel Standard TS68302VA16 Atmel Standard TS68302MA16 Atmel Standard Note: 1. Gullwing leads. Type Temperature range -55, +125°C V: -40, +85° +70°C Package: R: Pin Grid Array 132 ...
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... Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...