TS68EN360MAB Atmel Corporation, TS68EN360MAB Datasheet - Page 35
TS68EN360MAB
Manufacturer Part Number
TS68EN360MAB
Description
32-bit Communication Controller, 25 or 33 MHz
Manufacturer
Atmel Corporation
Datasheet
1.TS68EN360MAB.pdf
(83 pages)
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7.8
Table 7-7.
2113B–HIREL–06/05
Number
103C
103D
103A
103B
105A
111A
111
100
101
102
104
105
106
107
108
109
110
113
114
115
116
117
119
120
121
122
123
124
125
1
Bus Operation – DRAM Accesses AC Timing Specification
Characteristic
RASx Asserted to Row Address Invalid
RASx Asserted to column Address Valid
RASx Width Asserted
RASx width Negated (Back to back Cycle) Non page mode at
WBTQ = 0
RASx width Negated (Back to back Cycle) Page mode at WBTQ = 0
RASx width Negated (Back to back Cycle) Non page mode at
WBTQ = 1
RASx width Negated (Back to back Cycle) Page mode at WBTQ = 1
RASx Asserted to CASx Asserted
CLKO1 Low to CASx Asserted
CLKO1 High to CASx Asserted (Refresh Cycle)
CLKO1 High to CASx Negated
Column Address Valid to CASx Asserted
CASx Asserted to Column Address Negated
CASx Asserted to RASx Negated
CASx Width Asserted
CASx Width Negated (Back to Back Cycles)
CASx Width Negated (Page Mode)
WE Low to CASx Asserted
CASx Asserted to WE Negated
R/W Low to CASx Asserted (Write)
CASx Asserted to R/W High (Write)
Data-Out, Parity-Out Valid to CASx Asserted
CLKO1 High to AMUX Negated
CLKO1 High to AMUX Asserted
AMUX High to RASx Asserted
RASx Asserted to AMUX Low
AMUX Low to CASx Asserted
CASx Asserted to AMUX High
RAS/CASx Negated to R/W change
GND = 0 V
7-20
to
Figure
DC
, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See
7-24)
52.5
Min
115
15
20
75
75
55
95
35
15
40
35
50
95
20
35
35
55
10
15
15
15
55
3
3
3
3
3
0
25.0 MHz
Max
13
13
13
16
16
11.25
56.25
56.25
41.25
86.25
69.23
26.25
11.25
71.25
41.25
11.25
11.25
11.25
41.25
37.5
Min
7.5
15
30
27
15
27
27
40
2
2
2
2
2
0
TS68EN360
33.34 MHz
Max
10
10
10
12
12
Figure
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
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