N02L63W2A ON Semiconductor, N02L63W2A Datasheet
N02L63W2A
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N02L63W2A Summary of contents
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... Ultra-Low Power Asynchronous CMOS SRAM 128K × 16 bit Overview The N02L63W2A is an integrated memory device containing a 2 Mbit Static Random Access Memory organized as 131,072 words by 16 bits. The device is designed and fabricated using ON Semiconductor’s advanced CMOS technology to provide both high-speed performance and ultra-low power ...
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... N02L63W2A Pin Configuration PIN ONE I/O CE1 I I/O I I VCC 11 34 VSS VSS 12 E VCC I ...
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... N02L63W2A Functional Block Diagram Word Address Address Inputs Decode Logic Page Address Address Inputs Decode A4 - A16 Logic CE1 CE2 Control WE Logic Functional Description CE1 CE2 When UB and LB are in select mode (low), I/O are affected as shown ...
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... N02L63W2A Absolute Maximum Ratings Item Voltage on any pin relative to V Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time 1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied ...
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... N02L63W2A Power Savings with Page Mode Operation ( Page Address (A4 - A16) Word Address (A0 - A3) CE1 CE2 OE LB, UB Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature ...
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... N02L63W2A Timing Test Conditions Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Operating Temperature Timing Item Read Cycle Time Address Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output ...
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... N02L63W2A Timing of Read Cycle (CE1 = Address Previous Data Valid Data Out Timing Waveform of Read Cycle (WE=V Address CE1 CE2 OE LB, UB High-Z Data Out , WE = CE2 = OLZ LBLZ, UBLZ Rev Page www.onsemi.com www ...
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... N02L63W2A Timing Waveform of Write Cycle (WE control) Address CE1 CE2 LB High-Z Data In Data Out Timing Waveform of Write Cycle (CE1 Control) Address CE1 (for CE2 Control, use inverted signal) LB Data In Data Out LBW UBW ...
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... N02L63W2A 44-Lead TSOP II Package (T44) 10.16±0.13 0.80mm REF DETAIL B 0.20 0.00 Note: 1. All dimensions in inches (Millimeters) 2. Package dimensions exclude molding flash 18.41±0.13 11.76±0.20 0.45 0.30 1.10±0.15 0.80mm REF Rev Page www.onsemi.com www.DataSheet4U.com SEE DETAIL ...
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... N02L63W2A Ball Grid Array Package D A1 BALL PAD CORNER (3) TOP VIEW K TYP J TYP BOTTOM VIEW Dimensions (mm 6±0.10 8±0.10 0.375 0.28±0.05 1.24±0.10 E SIDE VIEW 1. DIMENSION IS MEASURED AT THE A1 BALL PAD SD MAXIMUM SOLDER BALL DIAMETER. CORNER PARALLEL TO PRIMARY Z. 2. PRIMARY DATUM Z AND SEATING ...
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... Part Number Package N02L63W2AT5I Leaded 44-TSOP II N02L63W2AT25I Green 44-TSOP II (RoHS Compliant) N02L63W2AB5I Leaded 48-BGA N02L63W2AB25I Green 48-BGA (RoHS Compliant) N02L63W2AT5IT Leaded 44-TSOP II N02L63W2AT25IT Green 44-TSOP II (RoHS Compliant) N02L63W2AB5IT Leaded 48-BGA N02L63W2AB25IT Green 48-BGA (RoHS Compliant) Revision History Revision Date A Jan. 2001 B ...