AD5235 Analog Devices, AD5235 Datasheet - Page 5

• Manufacturer Part Number: AD5235
• Description: 8-Bit Dual Nonvolatile Memory Digital Potentiometer
• Manufacturer: Analog Devices

Nonvolatile Memory Digital Potentiometers
OPERATIONAL OVERVIEW
The AD5235 digital potentiometer is designed to operate as a true
variable resistor replacement device for analog signals that remain
within the terminal voltage range of V
voltage range is limited to a V
potentiometer allows both scratch pad register (RDAC register)
changes to be made, as well as 100,000 times of nonvolatile
electrically erasable memory (EEMEM) register operations. The
EEMEM update process takes approximately 20.2ms, during this
time the shift register is locked preventing any changes from taking
place. The RDY pin flags the completion of this EEMEM save.
The EEMEM retention is designed to last 10 years without refresh.
The scratch pad register can be changed incrementally by using the
software controlled Increment/Decrement instruction or the Shift
Left/Right instruction command. Once an Increment, Decrement or
Shift command has been loaded into the shift register, subsequent
CS strobes will repeat this command. This is useful for push button
control applications. Alternately the scratch pad register can be
programmed with any position value using the standard SPI serial
interface mode by loading the representative data word. The
scratch pad register can be loaded with the current contents of the
nonvolatile EEMEM register under the program control. At system
power ON, the default value of the scratch pad memory is the value
previously saved in the EEMEM register. The factory EEMEM
preset value is midscale 512
A serial data output pin is available for daisy chaining and for
readout of the internal register contents. The serial input data
register uses a 24-bit instruction/address/data WORD. The write-
protect (WP) pin provides a hardware EEMEM protection feature
disabling any changes of the present EEMEM contents.
SERIAL DATA INTERFACE
The AD5235 contains a four-wire SPI compatible digital interface
(SDI, SDO, CS, and CLK). Key features of this interface include:
Table 1. AD5235 24-bit Serial Data Word
AD5235
Command bits are identified as Cx, address bits are Ax, and data bits are Dx. Command instruction codes are defined in table 2.
REV PrD 6 NOV, 2000
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL[phone]; FAX [phone]; [e-mail]
Independently Programmable Read & Write to all registers
Direct parallel refresh of all RDAC wiper registers from
corresponding EEMEM registers
M
S
B
C3
C2
C1
10
C0
.
DD
- V
PRELIMINARY TECHNICAL DATA
A3
SS
SS
<5.5V. Control of the digital
A2
<V
TERM
A1
<V
A0
DD
. The basic
X
X
X
5
X
The serial interface of AD5235 digital potentiometer uses a 24-bit
serial word loaded with MSB first. The format of the SPI
compatible word is shown in Table 1. The Command Bits (Cx)
control the operation of the digital potentiometer according to the
command instruction shown in Table 2. The Address Bits (Ax)
determine which register is activated. The Data Bits (Dx) are the
values that are loaded into the decoded register. The last
instruction executed prior to a period of no programming activity
should be the NOP instruction. This will place the internal logic
circuitry in a minimum power dissipation state.
The equivalent serial data input and output logic is shown in figure
2. The open drain output SDO is disabled whenever chip select CS
is logic high. The SPI interface can be used in two slave modes
CPHA=1, CPOL=1 and CPHA=0, CPOL=0. CPHA and CPOL
refer to the control bits, which dictate SPI timing in the following
microprocessors/MicroConverters: ADuC812/824, M68HC11, and
MC68HC16R1/916R1.
X
C L K
S D I
C S
Permanent storage of the present scratch pad RDAC register
values into the corresponding EEMEM register
30 bytes of user addressable electrical-erasable memory
X
Figure 2. Equivalent Digital Input-Output Logic
D9
C O U N T E R
D8
C O M M A N D
V A L ID
D7
D6
R E G IS T E R
S E R IA L
P R O C E S S O R
P R
& A D D R E S S
D5
C O M M A N D
D E C O D E
D4
AD5235
D3
D2
S D O
G N D
+ 5 V
R
D1
P U L LU P
L
S
B
D0