AD5245 Analog Devices, AD5245 Datasheet - Page 5

• Manufacturer Part Number: AD5245
• Description: 256-Position I2C Compatible Digital Potentiometer
• Manufacturer: Analog Devices

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(V
Table 3.
Parameter
I
NOTES
1
2
3
4
5
6
7
8
9
10
ABSOLUTE MAXIMUM RATINGS
(T
Table 4.
Parameter
V
V
I
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (T
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Thermal Resistance
NOTES
1
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
2
MAX
Maximum terminal current is bounded by the maximum current handling of
Package power dissipation = (T
Typical specifications represent average readings at +25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
V
INL and DNL are measured at V
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
P
All dynamic characteristics use V
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
C INTERFACE TIMING CHARACTERISTICS
DD
A
See timing diagrams for locations of measured values.
AB
DISS
, V
A
DD
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
1
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
SU;STO
to GND
= V
= +25°C, unless otherwise noted.)
B
is calculated from (I
Fall Time of Both SDA and SCL Signals
Rise Time of Both SDA and SCL Signals
= +5V ± 10%, or +3V ± 10%; V
, V
Bus Free Time between STOP and START
DD
Low Period of SCL Clock
High Period of SCL Clock
W
, Wiper (V
Setup Time for Repeated START Condition
Setup Time for STOP Condition
Hold Time (Repeated START)
Data Setup Time
Data Hold Time
to GND
W
) = no connect.
2
θ
DD
JA
× V
: MSOP-10
DD
W
JMAX
). CMOS logic level inputs result in minimum power dissipation.
DD
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
= 5 V.
– T
A
)/θ
JMAX
JA
.
A
= V
)
6, 10
DD
; V
(Specifications Apply to All Parts)
Value
–0.3 V to +7 V
V
±20 mA
0 V to +7 V
–40°C to +125°C
150°C
–65°C to +150°C
300°C
230°C/W
DD
B
1
= 0 V; –40°C < T
Symbol
f
t
t
t
t
t
t
t
t
t
t
DD
SCL
1
2
3
4
5
6
7
8
9
10
= 5 V.
Rev. 0 | Page 5 of 16
A
Conditions
After this period, the first clock pulse is
generated.
< +125°C; unless otherwise noted.)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Min
1.3
0.6
1.3
0.6
0.6
100
0.6
DD
and V
Typ
B
= 0 V.
1
Max
400
50
0.9
300
300
AD5245
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs