LT1460-5 Linear Technology, LT1460-5 Datasheet - Page 6

• Manufacturer Part Number: LT1460-5
• Description: Micropower Precision Series Reference
• Manufacturer: Linear Technology

APPLICATIONS
LT1460-5
Longer Battery Life
Series references have a large advantage over older shunt
style references. Shunt references require a resistor from
the power supply to operate. This resistor must be chosen
to supply the maximum current that can ever be
demanded by the circuit being regulated. When the circuit
being controlled is not operating at this maximum current,
the shunt reference must always sink this current, result-
ing in high dissipation and short battery life.
The LT1460-5 series reference does not require a current
setting resistor and can operate with any supply voltage
from V
lated does not demand current, the LT1460-5 reduces its
dissipation and battery life is extended. If the reference is
not delivering load current it dissipates less than 1mW on
a 7.5V supply, yet the same configuration can deliver
20mA of load current when demanded.
Capacitive Loads
The LT1460-5 is designed to be stable with capacitive
loads. With no capacitive load, the reference is ideal for
fast settling or applications where PC board space is a
premium. The test circuit shown in Figure 1 is used to
measure the response time for various load currents and
load capacitors. The 1V step from 5V to 4V produces a
current step of 1mA or 100 A for R
Figure 2 shows the response of the reference with no load
capacitance.
The reference settles to 5mV (0.1%) in less than 2 s for a
100 A pulse and to 0.1% in 3 s with a 1mA step. When
load capacitance is greater than 0.01 F, the reference
begins to ring due to the pole formed with the output
impedance. Figure 3 shows the response of the reference
to a 1mA and 100 A load with a 0.01 F load capacitor.
Fast Turn-On
It is recommended to add a 0.1 F or larger input capacitor
to the input pin of the LT1460-5. This helps stability with
large load currents and speeds up turn-on. The LT1460-5
can start in 10 s, but it is important to limit the dv/dt of the
input. Under light load conditions and with a very fast
input, internal nodes overslew and this requires finite
recovery time. Figure 4 shows the result of no bypass
6
OUT
+ 0.9V to 20V. When the circuitry being regu-
U
INFORMATION
U
W
L
= 1k or R
U
L
= 10k.
V
IN
= 5V
0.1 F
V
V
V
V
V
V
C
V
OUT
OUT
GEN
GEN
OUT
OUT
IN
OUT
V
IN
Figure 1. Response Time Test Circuit
Figure 3. C
LT1460-5
Figure 4. C
Figure 2. C
10 s/DIV
2 s/DIV
20 s/DIV
L
V
= 0.01 F
OUT
IN
L
= 0
= 0
C
L
R
L
1460-5 F03
1460-5 F02
1460-5 F04
V
GEN
5V
4V
R
R
0V
R
R
5V
4V
7.5V
0V
L
L
L
L
= 1k
= 10k
= 10k
= 1k
1460-5 F01
5V
4V