LTC4012-2 Linear Technology Corporation, LTC4012-2 Datasheet - Page 23

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LTC4012-2

Manufacturer Part Number
LTC4012-2
Description
Multi-Chemistry Battery Charger
Manufacturer
Linear Technology Corporation
Datasheet
www.DataSheet4U.com
APPLICATIONS INFORMATION
FET Selection
Two external power MOSFETs must be selected for use
with the charger: an N-channel power switch (top FET)
and an N-channel synchronous rectifi er (bottom FET).
Peak gate-to-source drive levels are internally set to
about 5V. Consequently, logic-level FETs must be used.
In addition to the fundamental DC current, selection
criteria for these MOSFETs also include channel resis-
tance R
capacitance C
BV
Power dissipation for each external FET is given by:
where δ is the temperature dependency of R
ΔT is the temperature rise above the point specifi ed in
the FET data sheet for R
versely related to the internal LTC4012 top gate driver.
The term (1 + δΔT) is generally given for a MOSFET in the
form of a normalized R
but δ of 0.005/°C can be used as a suitable approxima-
tion for logic-level FETs if other data is not available.
C
characteristics. The constant k = 2 can be used in estimat-
ing top FET dissipation. The LTC4012 is designed to work
best with external FET switches with a total gate charge
at 5V of 15nC or less.
For V
improves with larger FETs, while for V
transition losses increase rapidly to the point that using
a topside NFET with higher R
actually provide higher effi ciency. If the charger will be
operated with a duty cycle above 85%, overall effi ciency
is normally improved by using a larger top FET.
RSS
DSS
P
P
D TOP
D BOT
(
(
CLP
= ΔQ
and switching characteristics such as t
DS(ON)
< 20V, high charge current effi ciency generally
)
)
=
=
GD
+
(
V
/ΔV
RSS
V
, total gate charge Q
BAT
k V
CLP
DS
, maximum rated drain-source voltage
C
I
is usually specifi ed in the MOSFET
MAX
L L P
V
BAT
DS(ON)
2
2
DS(ON)
)
I
V
MAX
CLP
(
1 δΔ
I
M
DS(ON)
+
curve versus temperature,
V
A A X
CLP
and k is a constant in-
C
2
T R
RSS
)
(
but lower C
G
1
CLP
, reverse transfer
DS ON
+
665
δΔ
(
> 20V, top gate
T R
)
kHz
)
DS ON
d(ON/OFF)
RSS
(
DS(ON)
)
can
.
,
The synchronous (bottom) FET losses are greatest at high
input voltage or during a short circuit, which forces a low
side duty cycle of nearly 100%. Increasing the size of this
FET lowers its losses but increases power dissipation in the
LTC4012. Using asymmetrical FETs will normally achieve
cost savings while allowing optimum effi ciency.
Select FETs with BV
voltage that will occur. Both FETs are subjected to this level
of stress during operation. Many logic-level MOSFETs are
limited to 30V or less.
The LTC4012 uses an improved adaptive TGATE and
BGATE drive that is insensitive to MOSFET inertial delays,
t
characteristics from power MOSFET data sheets apply
only to a specifi c test fi xture, so there is no substitute for
bench evaluation of external FETs in the target application.
In general, MOSFETs with lower inertial delays will yield
higher effi ciency.
Diode Selection
A Schottky diode in parallel with the bottom FET and/or
top FET in an LTC4012 application clamps SW during the
non-overlap times between conduction of the top and
bottom FET switches. This prevents the body diode of the
MOSFETs from forward biasing and storing charge, which
could reduce effi ciency as much as 1%. One or both diodes
can be omitted if the effi ciency loss can be tolerated. A 1A
Schottky is generally a good size for 3A chargers due to the
low duty cycle of the non-overlap times. Larger diodes can
actually result in additional effi ciency (transition) losses
due to larger junction capacitance.
Loop Compensation and Soft-Start
The three separate PWM control loops of the LTC4012
can be compensated by a single set of components at-
tached between the ITH pin and GND. As shown in the
typical LTC4012 application, a 6.04k resistor in series
with a capacitor of at least 0.1μF provides adequate loop
compensation for the majority of applications.
d(ON/OFF)
, to avoid overlap conduction losses. Switching
LTC4012-1/LTC4012-2
DSS
that exceeds the maximum V
LTC4012/
23
4012f
CLP

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