LTC4252-2 Linear Technology, LTC4252-2 Datasheet - Page 21

• Manufacturer Part Number: LTC4252-2
• Description: Negative Voltage Hot Swap Controllers
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
As seen in Figure 6 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramati-
cally owing to series inductance. If this voltage avalanches
the MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4252’s
V
drawing in Figure 8 illustrates the correct way of making
connections between the LTC4252 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
TIMING WAVEFORMS
System Power-Up
Figure 9 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
EE
and SENSE pins are strongly recommended. The
60
50
40
30
20
10
Figure 7. Recommended Compensation
Capacitor C
0
0
IRF540S
IRF530S
2000
U
IRF740
C
MOSFET C
vs MOSFET C
U
IRF3710
4000
ISS
NTY100N10
(pF)
6000
ISS
W
4252-1/2 F07
8000
U
time point 1, the supply ramps up, together with UV/OV,
V
as set by the V
exceeds V
OV < V
and TIMER < V
timing cycle starts and the TIMER capacitor is charged by
a 5.8µA current source pull-up. At time point 3, TIMER
reaches the V
terminates. The TIMER capacitor is quickly discharged. At
time point 4, the V
conditions of GATE < V
SS < 20 • V
cycle begins. SS ramps up as dictated by R
Equation 6); GATE is held low by the analog current limit
(ACL) amplifier until SS crosses 20 • V
GATE, 58µA sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
V
the load current. If the SENSE voltage (V
reaches the V
breaker TIMER activates. The TIMER capacitor, C
charged by a (230µA + 8 • I
capacitor nears full charge, load current begins to decline.
TRACK WIDTH W:
ON 1 OZ COPPER
0.03" PER AMP
OUT
ACL
Figure 8. Making PCB Connections to the Sense Resistor
(t) (Equation 7) and soft-start limits the slew rate of
and DRAIN. V
LTC4252A-1/LTC4252A-2
OVLO
CURRENT FLOW
LKO
FROM LOAD
, GATE < V
OS
LTC4252-1/LTC4252-2
and the internal logic checks for UV > V
TMRH
W
CB
must be satisfied before a GATE ramp-up
IN
TMRL
threshold at time point 7, the circuit
bypass capacitor. At time point 2, V
IN
threshold and the initial timing cycle
TMRL
. If all conditions are met, an initial
and PWRGD follow at a slower rate
GATEL
SENSE
TO
SENSE RESISTOR
DRN
threshold is reached and the
, SENSE < V
GATEL
) current pull-up. As the load
V
TO
EE
, SENSE < V
TO –48V BACKPLANE
OS
CB
CURRENT FLOW
. Upon releasing
, SS < 20 • V
SS
SENSE
• C
4252-1/2 F08
SS
21
CB
– V
425212fb
(as in
UVHI
T
and
, is
EE
OS
IN
)
,