LTC6992-4 Linear Technology, LTC6992-4 Datasheet - Page 12

• Manufacturer Part Number: LTC6992-4
• Description: TimerBlox Voltage-Controlled Pulse Width Modulator (PWM)
• Manufacturer: Linear Technology

PIN FUNCTIONS
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted.
V
ply must be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1μF capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. A V
pin voltage (V
V
and GND. Use 1% resistors to ensure an accurate result.
The DIV pin and resistors should be shielded from the
OUT pin or any other traces that have fast edges. Limit the
capacitance on the DIV pin to less than 100pF so that V
settles quickly. The MSB of DIVCODE (POL) determines
if the PWM signal is inverted before driving the output.
Setting POL = 1 results in a negative transfer function
(duty cycle decreasing as V
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (V
amount of current sourced from the SET pin (I
grams the master oscillator frequency. The I
range is 1.25μA to 20μA. The output oscillation will stop
12
+
DIV
(Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This sup-
may be generated by a resistor divider between V
+
referenced A/D converter monitors the DIV
DIV
1V/DIV
1V/DIV
OUT
) to determine a 4-bit result (DIVCODE).
V
SET
+
V
DIVCODE = 3 (÷64)
R
V
Typical Start-Up, POL = 0
+
MOD
SET
) is regulated to 1V above GND. The
= 2.5V
= 50k
= 0.3V (~25% DUTY CYCLE)
MOD
(DCB/S6)
500μs
100μs/DIV
increases).
6992 G53
SET
SET
current
) pro-
DIV
+
if I
nected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
50ppm/°C or better temperature coefficient. For lower ac-
curacy applications an inexpensive 1% thick film resistor
may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the V
SET
1V/DIV
1V/DIV
OUT
V
+
drops below approximately 500nA. A resistor con-
V
DIVCODE = 12 (÷64, POL = 1)
R
V
Typical Start-Up, POL = 1
+
MOD
SET
= 2.5V
= 50k
= 0.2V (~87.5% DUTY CYCLE)
V
+
= 3.3V, R
SET
V
+
R
500μs
100μs/DIV
SET
voltage.
MOD
GND
SET
SET
LTC6992
= 200k, and T
OUT
6992 PF
DIV
V
+
6992 G54
www.DataSheet4U.com
C1
0.1μF
A
= 25°C, unless
V
+
R1
R2
69921234p