LTC6994-2 Linear Technology Corporation, LTC6994-2 Datasheet - Page 18

• Manufacturer Part Number: LTC6994-2
• Description: Delay Block / Debouncer
• Manufacturer: Linear Technology Corporation

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LTC6994-1/LTC6994-2
applicaTions inForMaTion
Settling Time
Following a 2× or 0.5× step change in I
put delay takes approximately six master clock cycles
(6 • t
An example is shown in Figure 12, using the circuit in
Figure 10.
Coupling Error
The current sourced by the SET pin is used to bias the in-
ternal master oscillator. The LTC6994 responds to changes
in I
settling time. However, this fast response also makes the
SET pin sensitive to coupling from digital signals, such
as the IN input.
Even an excellent layout (examples are provided in the
next section) will allow some coupling between IN and
SET that can affect fast output pulses. Additional error is
included in the specified accuracy for N
for this.
A very poor layout can actually degrade performance
further. The PCB layout should avoid routing SET next to
IN (or any other fast-edge, wide-swing signal).

SET
2µs/DIV
MASTER
2V/DIV
5V/DIV
5V/DIV
DELAY
V
CTRL
OUT
almost immediately, which provides excellent
IN
LTC6994-1
V
DIVCODE = 0
R
R
t
OUT
+
SET
MOD
= 3.3V
) to settle to within 1% of the final value.
= 3µs AND 6µs
= 200k
Figure 12. Typical Settling Time
= 464k
20µs/DIV
DIV
699412 F12
= 1 to account
SET
, the out-
699412p