OM4085 Philips Semiconductors, OM4085 Datasheet - Page 21

• Manufacturer Part Number: OM4085
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 7 LCD bias configuration
Table 8 Display status
Table 9 Power dissipation mode
Table 10 Load data pointer
Table 11 Device select
Table 12 Input bank selection
Table 13 Output bank selection
Table 14 Blinking frequency
1997 Feb 25
1
1
Disabled (blank)
Enabled
Normal mode
Power-saving mode
RAM bit 0
RAM bit 2
RAM bit 0
RAM bit 2
Off
2 Hz
1 Hz
0.5 Hz
FREQUENCY
3
2
Universal LCD driver for low multiplex
rates
bias
bias
BITS
DISPLAY STATUS
STATIC
STATIC
BLINK
LCD BIAS
MODE
BITS
5-bit binary value of 0 to 23
3-bit binary value of 0 to 7
P4
RAM bits 0, 1
RAM bits 2, 3
RAM bits 0, 1
RAM bits 2, 3
1 : 2 MUX
1 : 2 MUX
BIT BF1
P3
0
0
1
1
A0
P2
BIT LP
BIT B
BIT E
A1
0
1
0
1
0
1
P1
BIT BF0
BIT 1
BIT 0
0
1
0
1
0
1
0
1
A2
P0
21
Table 15 Blink mode selection
Display controller
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the OM4085 and coordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.
Cascaded operation
In large display configurations, up to 16 OM4085s can be
distinguished on the same I
hardware subaddress (A0, A1 and A2) and the
programmable I
possible to cascade up to 16 OM4085s. When cascaded,
several OM4085s are synchronized so that they can share
the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the outputs of only one device
need to be through-plated to the backplane electrodes of
the display. The other OM4085s of the cascade contribute
additional segment outputs but their backplane outputs are
left open-circuit (Fig.17).
The SYNC line is provided to maintain the correct
synchronization between all cascaded OM4085s.
This synchronization is guaranteed after the power-on
reset. The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when OM4085s with differing SA0 levels
are cascaded). SYNC is organized as an input/output pin;
the output section being realized as an open-drain driver
with an internal pull-up resistor. A OM4085 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times.
Should synchronization in the cascade be lost, it will be
restored by the first OM4085 to assert SYNC. The timing
relationships between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8576
are shown in Fig.18. The waveforms are identical with the
parent device PCF8576. Cascade ability between
OM4085s and PCF8576s is possible, giving cost effective
LCD applications.
Normal blinking
Alternation blinking
BLINK MODE
2
C-bus slave address (SA0). It is also
2
C-bus by using the 3-bit
Product specification
BIT A
OM4085
0
1