MX26C512A Macronix International, MX26C512A Datasheet - Page 3

• Manufacturer Part Number: MX26C512A
• Description: CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
• Manufacturer: Macronix International

P/N: PM0455
other address lines must be held at VIL during auto identify
mode.
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For
the MX26C512A, these two identifier bytes are given in
the Mode Select Table. All identifiers for the manufacturer
and device codes will possess odd parity, with the MSB
(DQ7) defined as the parity bit.
READ MODE
The MX26C512A has two control functions, both of
which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC - tOE.
STANDBY MODE
The MX26C512A has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is placed
in CMOS standby when CE is at VCC ± 0.3 V. The
MX26C512A also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is placed
in TTL-standby when CE is at VIH. When in standby
mode, the outputs are in a high-impedance state,
independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
Patent#: US#5,523,307
3
memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions,
transient current peaks are produced on the rising and
falling edges of Chip Enable. The magnitude of these
transient current peaks is dependent on the output
capacitance loading of the device. At a minimum, a 0.1
uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be used
between VCC and GND for each of the eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.
MX26C512A
REV.1.8, JUL. 13 , 1998
INDEX