MX29LV800BT Macronix, MX29LV800BT Datasheet
MX29LV800BT
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MX29LV800BT Summary of contents
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... Status Reply - Data# polling & Toggle bit for detection of program GENERAL DESCRIPTION The MX29LV800BT/ 8-mega bit Flash memory organized as 1M bytes of 8 bits or 512K words of 16 bits. MXIC's Flash memories offer the most cost-effec- tive and reliable read/write non-volatile random access memory ...
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... A10 Q15/A-1 A11 A12 CE# A13 A14 WE# A15 A16 BYTE# BYTE# RESET# GND Q15/A-1 OE# Q7 Q14 RY/BY# Q6 Q13 VCC Q5 Q12 GND Q4 VCC MX29LV800BT/ A15 A16 BYTE# Q15/A-1 GND A11 Q7 Q14 Q13 NC Q5 Q12 Vcc NC Q2 Q10 Q11 CE# ...
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... BLOCK STRUCTURE TABLE 1: MX29LV800BT SECTOR ARCHITECTURE Sector Sector Size Byte Mode Word Mode SA0 64Kbytes 32Kwords SA1 64Kbytes 32Kwords SA2 64Kbytes 32Kwords SA3 64Kbytes 32Kwords SA4 64Kbytes 32Kwords SA5 64Kbytes 32Kwords SA6 64Kbytes 32Kwords SA7 64Kbytes 32Kwords SA8 64Kbytes 32Kwords SA9 ...
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... SA15 64Kbytes 32Kwords SA16 64Kbytes 32Kwords SA17 64Kbytes 32Kwords SA18 64Kbytes 32Kwords Note: Byte mode:address range A18:A-1, word mode:address range A18:A0. P/N:PM1062 MX29LV800BT/BB Address range Byte Mode (x8) Word Mode (x16) 00000h-03FFFh 00000h-01FFFh 04000h-05FFFh 02000h-02FFFh 06000h-07FFFh 03000h-03FFFh 08000h-0FFFFh 04000h-07FFFh 10000h-1FFFFh 08000h-0FFFFh 20000h-2FFFFh ...
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... BLOCK DIAGRAM CONTROL CE# OE# INPUT WE# LOGIC RESET# ADDRESS LATCH A0-A18 AND BUFFER Q0-Q15/A-1 P/N:PM1062 MX29LV800BT/BB PROGRAM/ERASE HIGH VOLTAGE MX29LV800BT/BB FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 5 WRITE STATE MACHINE (WSM) STATE REGISTER COMMAND DATA ...
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... Automatic Programming algorithm. The Automatic Pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV800BT/BB is less than 10 seconds. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the ...
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... Table 1 and Table 2). The rest of address bits, as shown in table 3, are don't care. Once all necessary bits have been set as required, the pro- gramming equipment may read the corresponding iden- tifier code on Q7~Q0. TABLE 3. MX29LV800BT/BB AUTO SELECT MODE OPERATION Description Mode CE# OE# WE# Manufacturer Code Read ...
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... QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE ( for MX29LV800BT/ BB) MX29LV800BT/BB is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating param- eters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode ...
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... Erase suspend (2= to read and write) Sector protect ( sectors/group) Temporary sector unprotected (1=supported) Sector protect/unprotected scheme Simultaneous R/W operation (0=not supported) Burst mode type (0=not supported) Page mode type (0=not supported) P/N:PM1062 MX29LV800BT/BB Address Address (Byte Mode) (Word Mode ...
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... TABLE 5. MX29LV800BT/BB COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH F0H Read 1 RA Read Silicon ID Word 4 555H AAH 2AAH Byte 4 AAAH AAH 555H Sector Protect Word 4 555H AAH 2AAH Verify Byte 4 AAAH AAH 555H Program Word 4 555H AAH 2AAH ...
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... Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 5 defines the valid register command TABLE 6. MX29LV800BT/BB BUS OPERATION DESCRIPTION CE# OE# WE# RESET# A18 A10 A9 Read ...
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... Q7-Q0. Standard read cycle timings apply in this mode. P/N:PM1062 MX29LV800BT/BB Refer to the Autoselect Mode and Autoselect Command Sequence section for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The " ...
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... ID command sequence into the command regis- ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of DAH/22DAH for MX29LV800BT, 5BH/ 225BH for MX29LV800BB. P/N:PM1062 MX29LV800BT/BB ...
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... TABLE 7. SILICON ID CODE Pins A0 Manufacture code Word VIL Byte VIL Device code Word VIH for MX29LV800BT Byte VIH Device code Word VIH for MX29LV800BB Byte VIH Sector Protection Word X Verification Byte X READING ARRAY DATA The device is automatically set to reading array data after device power-up ...
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... Another Erase Suspend command can be written after the chip has resumed erasing. However, a delay time must be required after the erase resume command (1.5ms for MX29LV800BT/BB), if the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times. The erase times will be expended if the erase behavior always be suspended ...
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... During the Automatic Erase algorithm, DATA# polling pro- duces a "0" on Q7. When the Automatic Erase algo- P/N:PM1062 MX29LV800BT/BB rithm is complete the device enters the Erase Sus- pend mode, DATA# polling produces a "1" on Q7. This is analogous to the complement/true datum out-put de- scribed for the Automatic Program algorithm: the erase function changes all the bits in a sector to " ...
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... OE# or CE# to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com- P/N:PM1062 MX29LV800BT/BB parison, indicates whether the device is actively eras- ing Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information ...
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... Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information. P/N:PM1062 MX29LV800BT/BB If this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- ...
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... In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be- tween its VCC and GND. POWER-UP SEQUENCE The MX29LV800BT/BB powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. ...
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... Performing a read operation with A1=VIH, it will produce a logical "1" for the protected sector. CHIP UNPROTECTED The MX29LV800BT/BB also features the chip unpro- tected mode, so that all sectors are unprotected after chip unprotected is completed to incorporate any changes in the code recommended to protect all sectors before activating chip unprotected mode ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. P/N:PM1062 MX29LV800BT/BB OPERATING RATINGS Commercial (C) Devices +150 C ...
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... VIH max. = VCC + 1.5V for pulse width is equal to or less than VIH is over the specified maximum value, read operation cannot be guaranteed. 3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns. P/N:PM1062 MX29LV800BT/BB MIN. TYP MAX. ...
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... Input rise and fall times is equal to or less than 5ns. • Output load: 1 TTL gate + 100pF (Including scope and jig), for 29LV800T/B-90. 1 TTL gate + 30pF (Including scope and jig) for 29LV800BT/BB-70 • Reference levels for measuring timing: 1.5V. P/N:PM1062 MX29LV800BT/ VCC = 2.7V~3.6V 29LV800BT/BB-70 29LV800BT/BB-90 MIN ...
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... AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. P/N:PM1062 MX29LV800BT/BB CL 6.2K ohm CL= 100pF Including jig capacitance (30pF for MX29LV800BT/BB-70) TEST POINTS INPUT 24 2.7K ohm +3.3V DIODES=IN3064 OR EQUIVALENT OUTPUT REV. 1.3, DEC. 20, 2004 ...
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... FIGURE 1. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE# VIL VIH WE# VIL VIH OE# VIL HIGH Z VOH Outputs VOL VIH RESET# VIL P/N:PM1062 MX29LV800BT/BB tRC ADD Valid tACC tCE tOE tOEH tACC tOH DATA Valid 25 tDF HIGH Z REV. 1.3, DEC. 20, 2004 ...
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... Write Pulse Width for Sector Protect (A9, OE# Control) tWPP2 Write Pulse Width for Chip Unprotected (A9, OE# Control) tBAL Sector Address Load Time NOTES: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. P/N:PM1062 MX29LV800BT/ VCC = 2.7V~3.6V 29LV800BT/BB-70 MIN. MAX ...
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... WE# Hold Time tCP CE# Pulse Width tCPH CE# Pulse Width High tWHWH1 Programming Operation(note2) tWHWH2 Sector Erase Operation (note2) NOTE: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. P/N:PM1062 MX29LV800BT/ VCC = 2.7V~3.6V 29LV800BT/BB-70 MIN. MAX ...
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... FIGURE 2. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE# VIL tOES CE# VIH VIL tCS OE# VIH VIL VIH Data VIL P/N:PM1062 MX29LV800BT/BB ADD Valid tAH tWPH tWP tCWC tCH tDS tDH DIN 28 REV. 1.3, DEC. 20, 2004 ...
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... VCC NOTES: 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address P/N:PM1062 MX29LV800BT/BB ing after automatic programming starts. Device outputs DATA# during programming and DATA# after program- ming on Q7. (Q6 is for toggle bit; see toggle bit, DATA# polling, timing waveform) ...
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... FIGURE 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM1062 MX29LV800BT/BB START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? YES No Last Address ? YES Auto Program Completed 30 REV ...
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... Data tRH RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. 2.Figure indicates the last two bus cycles of the command sequence. P/N:PM1062 MX29LV800BT/BB PA for program SA for sector erase 555 for chip erase Data Polling tAS tAH tCP tWHWH1 or 2 ...
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... VCC NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status"). P/N:PM1062 MX29LV800BT/BB matic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle bit, DATA# polling, timing waveform) Read Status Data ...
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... FIGURE 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM1062 MX29LV800BT/BB START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data Pall from System ...
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... NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status"). P/N:PM1062 MX29LV800BT/BB ing after automatic erase starts. Device outputs 0 dur- ing erasure and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle bit, DATA# polling, timing waveform) ...
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... FIGURE 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM1062 MX29LV800BT/BB START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address NO Last Sector ...
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... FIGURE 10. ERASE SUSPEND/ERASE RESUME FLOWCHART Note the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times, then the delay time must be put into consideration. 2. Delay timing: 1.5ms for MX29LV800BT/BB. P/N:PM1062 MX29LV800BT/BB START Write Data B0H ERASE SUSPEND ...
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... FIGURE 11. IN-SYSTEM SECTOR PROTECT/UNPROTECTED TIMING WAVEFORM (RESET# Control) VID VIH RESET# SA, A6 A1, A0 Sector Protect or Chip Unprotect Data 60h 1us CE# WE# OE# Note: When sector protect, A6=0, A1=1, A0=0. When chip unprotect, A6=1, A1=1, A0=0. P/N:PM1062 MX29LV800BT/BB Valid* Valid* Verify 60h 40h Sector Protect =150us Chip Unprotect =15ms 37 Valid* Status REV. 1.3, DEC. 20, 2004 ...
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... FIGURE 12. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control 12V 3V A9 tVLHT 12V 3V OE# tVLHT WE# CE# Data A18-A12 P/N:PM1062 MX29LV800BT/BB tWPP 1 tOESP Sector Address 38 Verify tVLHT 01H F0H tOE REV. 1.3, DEC. 20, 2004 ...
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... FIGURE 13. SECTOR PROTECTION ALGORITHM (A9, OE# Control) No PLSCNT=32? Yes Device Failed P/N:PM1062 MX29LV800BT/BB START Set Up Sector Addr PLSCNT=1 OE#=VID, A9=VID, CE#=VIL A6=VIL Activate WE# Pulse Time Out 150us Set WE#=VIH, CE#=OE#=VIL A9 should remain VID Read from Sector Addr=SA, A1=1 No Data=01H? Yes Protect Another Sector? ...
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... FIGURE 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID Increment PLSCNT No PLSCNT=25? Yes Device failed P/N:PM1062 MX29LV800BT/BB START PLSCNT=1 RESET#=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H Yes Set up sector address Write 60H to sector address with A6=0, A1=1, A0=0 Wait 150us Verify sector protect : ...
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... FIGURE 15. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET#=VID Increment PLSCNT No PLSCNT=1000? Yes Device failed P/N:PM1062 MX29LV800BT/BB START PLSCNT=1 RESET#=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H ? Yes No All sector Protect all sectors protected? Yes Set up first sector address ...
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... A18-A12 Notes: tVLHT (Voltage transition time)=4us min. tWPP1 (Write pulse width for sector protect)=100ns min, 10us(Typ.) tWPP2 (Write pulse width for chip unprotected)=100ns min, 12ms(Typ.) tOESP (OE# setup time to WE# active)=4us min. P/N:PM1062 MX29LV800BT/BB tWPP 2 tOESP 42 Verify tVLHT ...
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... FIGURE 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control) Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1062 MX29LV800BT/BB START Protect All Sectors PLSCNT=1 Set OE#=A9=VID CE#=VIL,A6=1 Activate WE# Pulse Time Out 50ms Set OE#=CE#=VIL A9=VID,A1=1 Set Up First Sector Addr ...
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... WRITE OPERATION STATUS FIGURE 18. DATA# POLLING ALGORITHM NOTE : 1.VA=Valid address for programming 2.Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1062 MX29LV800BT/BB Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? Yes Read Q7~Q0 Add.=VA Yes Q7 = Data ? (2) No FAIL 44 Pass REV. 1.3, DEC. 20, 2004 ...
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... FIGURE 19. TOGGLE BIT ALGORITHM NO Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM1062 MX29LV800BT/BB Start Read Q7-Q0 Read Q7-Q0 (Note 1) NO Toggle Bit Q6 = Toggle ? YES Q5= 1? YES Read Q7~Q0 Twice (Note 1,2) ...
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... WE# DQ7 Q0-Q6 tBUSY RY/BY# NOTES: 1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle. 2. CE# must be toggled when DATA# polling. P/N:PM1062 MX29LV800BT/BB VA tDF tOH Complement Complement True Status Data Status Data True ...
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... RY/BY# NOTES: 1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 2. CE# must be toggled when toggle bit toggling. P/N:PM1062 MX29LV800BT/BB VA tDF tOH Valid Status Valid Status (second read) ...
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... RY/BY# Recovery Time (to CE#, OE# go low) Note: Not 100% tested FIGURE 22. RESET# TIMING WAVEFORM RY/BY# CE#, OE# RESET# Reset Timing NOT during Automatic Algorithms RY/BY# CE#, OE# RESET# Reset Timing during Automatic Algorithms P/N:PM1062 MX29LV800BT/BB Test Setup All Speed Options Unit MAX MAX tRH tRP tReady2 tReady1 tRP ...
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... BYTE# Switching Low to Output HIGH Z tFHQV BYTE# Switching High to Output Active FIGURE 23. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to word mode) CE# OE# BYTE# Q0~Q14 Q15/A-1 P/N:PM1062 MX29LV800BT/BB Max Max Min tELFH DOUT (Q0-Q7) (Q0-Q14) DOUT VA (Q15) tFHQV 49 ...
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... BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from word mode to byte mode) CE# OE# BYTE# Q0~Q14 Q15/A-1 FIGURE 25. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS CE# WE# BYTE# P/N:PM1062 MX29LV800BT/BB tELFH DOUT (Q0-Q14) DOUT VA (Q15) tFLQZ The falling edge of the last WE# signal tAS tAH 50 DOUT (Q0-Q7) REV ...
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... Erasing Suspend Erase WE NOTES: The system can use toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended P/N:PM1062 MX29LV800BT/BB Test Setup All Speed Options Unit Min Min Program or Erase Command Sequence Enter Erase Suspend Program Resume Erase Erase Suspend ...
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... FIGURE 28. TEMPORARY SECTOR UNPROTECTED ALGORITHM Temporary Sector Unprotect Completed(Note 2) Note : 1. All protected sectors are temporary unprotected. P/N:PM1062 MX29LV800BT/BB Start RESET# = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET# = VIH VID=11.5V~12.5V 2. All previously protected sectors are protected again. 52 REV. 1.3, DEC. 20, 2004 ...
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... VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A18 VIL CE# VIH VIL tCE VIH WE# VIL VIH OE# VIL VIH DATA VIL Q0-Q15 P/N:PM1062 MX29LV800BT/BB tACC tOE tOH DATA OUT C2H/00C2H 53 tDF tOH DATA OUT DAH/5BH (Byte) 22DAH/225BH (Word) REV. 1.3, DEC. 20, 2004 ...
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... Input Voltage with respect to GND on ACC, OE#, RESET#, A9 Input Voltage with respect to GND on all power pins, Address pins, CE# and WE# Input Voltage with respect to GND on all I/O pins Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N:PM1062 MX29LV800BT/BB LIMITS MIN. TYP.(2) MAX.(3) 0.7 ...
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... MX29LV800BTMC-70 70 MX29LV800BBMC-70 70 MX29LV800BTMC-90 90 MX29LV800BBMC-90 90 MX29LV800BTTC-70 70 MX29LV800BBTC-70 70 MX29LV800BTTC-90 90 MX29LV800BBTC-90 90 MX29LV800BTXBC-70 70 MX29LV800BTXBC-90 90 MX29LV800BBXBC-70 70 MX29LV800BBXBC-90 90 MX29LV800BTMI-70 70 MX29LV800BBMI-70 70 MX29LV800BTMI-90 90 MX29LV800BBMI-90 90 MX29LV800BTTI-70 70 MX29LV800BBTI-70 70 MX29LV800BTTI-90 90 MX29LV800BBTI-90 90 MX29LV800BTXBI-70 70 MX29LV800BTXBI-90 90 MX29LV800BBXBI-70 70 MX29LV800BBXBI-90 90 P/N:PM1062 MX29LV800BT/BB OPERATING STANDBY Current MAX. (mA) Current MAX. (uA ...
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... PART NO. ACCESS TIME (ns) MX29LV800BTXEC-70 70 MX29LV800BTXEC-90 90 MX29LV800BBXEC-70 70 MX29LV800BBXEC-90 90 MX29LV800BTXEI-70 70 MX29LV800BTXEI-90 90 MX29LV800BBXEI-70 70 MX29LV800BBXEI-90 90 MX29LV800BTTC-70G 70 MX29LV800BBTC-70G 70 MX29LV800BTTC-90G 90 MX29LV800BBTC-90G 90 MX29LV800BTXBC-70G 70 MX29LV800BTXBC-90G 90 MX29LV800BBXBC-70G 70 MX29LV800BBXBC-90G 90 MX29LV800BTTI-70G 70 MX29LV800BBTI-70G 70 MX29LV800BTTI-90G 90 MX29LV800BBTI-90G 90 P/N:PM1062 MX29LV800BT/BB OPERATING STANDBY Current MAX. (mA) Current MAX. (uA ...
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... PART NO. ACCESS TIME (ns) MX29LV800BTXBI-70G 70 MX29LV800BTXBI-90G 90 MX29LV800BBXBI-70G 70 MX29LV800BBXBI-90G 90 MX29LV800BTXEC-70G 70 MX29LV800BTXEC-90G 90 MX29LV800BBXEC-70G 70 MX29LV800BBXEC-90G 90 MX29LV800BTXEI-70G 70 MX29LV800BTXEI-90G 90 MX29LV800BBXEI-70G 70 MX29LV800BBXEI-90G 90 P/N:PM1062 MX29LV800BT/BB OPERATING STANDBY Current MAX. (mA) Current MAX. (uA PACKAGE Remark 48 Ball CSP PB free (Ball Size:0 ...
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... PACKAGE INFORMATION P/N:PM1062 MX29LV800BT/BB 58 REV. 1.3, DEC. 20, 2004 ...
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... P/N:PM1062 MX29LV800BT/BB 59 REV. 1.3, DEC. 20, 2004 ...
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... CSP (for MX29LV800BTXBC/BTXBI/BBXBC/BBXBI) P/N:PM1062 MX29LV800BT/BB 60 REV. 1.3, DEC. 20, 2004 ...
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... CSP (for MX29LV800BTXEC/BTXEI/BBXEC/BBXEI) P/N:PM1062 MX29LV800BT/BB 61 REV. 1.3, DEC. 20, 2004 ...
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... REVISION HISTORY Revision No. Description 1 corrected data retention information 2. Removed "Advanced Information" 1 corrected CFI Query command address 1.2 1. Added MX29LV800BTXEI/BBXEI-70/90 & MX29LV800BTXEC/ BBXEC/BTXEI/BBXEI-70G/90G in Ordering Information 1 corrected tRC definition from MAX. to MIN. P/N:PM1062 MX29LV800BT/BB Page P1,54 P1 P10 P56,57 P23 62 Date MAY/28/2004 ...
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... MX29LV800BT/BB MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...