fs7140 ON Semiconductor, fs7140 Datasheet
fs7140
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fs7140 Summary of contents
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... Via the I FS7140/45 can be adapted to many clock generation requirements. The length of the reference and feedback dividers, their fine granularity and the flexibility of the post divider make the FS7140/45 the most flexible stand−alone PLL clock generator available. Features • ...
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... Crystal oscillator feedback Crystal oscillator drive Address select bit “1” Power supply (+3.3 V nominal) PECL current drive programming No connection Ground Reference frequency input FS7140 = No connection FS7145 = Synchronization input Power supply (+3.3 V nominal) Clock output Inverted clock output U = Input with Internal Pull−up; DI http://onsemi.com 2 = Input with Internal Pull− ...
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Table 2. ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply voltage ground Input voltage Output voltage Input clamp current < Output ...
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Table 4. DC ELECTRICAL SPECIFICATIONS Parameter Symbol OVERALL Supply current, dynamic Supply current, static SERIAL COMMUNICATION I/O (SDA, SCL) High−level input voltage Low−level input voltage Hysteresis voltage Input leakage current Low−level output sink current (SDA) ADDRESS SELECT INPUT (ADDR0, ADDR1) ...
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Table 4. DC ELECTRICAL SPECIFICATIONS Parameter Symbol CLOCK OUTPUTS, CMOS MODE (CLKN, CLKP) Low−level output sink current CLOCK OUTPUTS, PECL MODE (CLKN, CLKP) IPRG bias voltage IPRG bias current Sink current to IPRG current ratio Tristate output current 1. Unless ...
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Table 6. SERIAL INTERFACE TIMING SPECIFICATIONS Parameter Clock frequency Bus free time between STOP and START Set−up time, START (repeated) Hold time, START Set−up time, data input Hold time, data input Output data valid from clock Rise time, data and ...
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... See Table 12 for additional information. Crystal Oscillator The FS7140 is equipped with a Pierce−type crystal oscillator. The crystal is operated in parallel resonant mode. Internal load capacitance is provided for the crystal. While a recommended load capacitance for the crystal is specified, ...
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... C−bus where X is controlled by the logic level at the ADDR pins. The selectable ADDR bits allow four different FS7140 devices to exist on the same bus. Note that every device C−bus must have a unique address to avoid possible bus conflicts. Random Register Write Procedure Random write operations allow the master to directly write to any register ...
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If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored. Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform ...
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Figure 3. Random Register Write Procedure Figure 4. Random Register Read Procedure Figure 5. Sequential Register Write Procedure Figure 6. Sequential Register Read Procedure http://onsemi.com 10 ...
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... Programming Information All register bits are cleared to zero on power−up. All register bits may be read back as written. Table 7. FS7140 REGISTER MAP Address BIT 7 BIT 6 Byte 7 Reserved Reserved (Bit 63) (Bit 62) Must be set Must be set to “0” to “0” Byte 6 Reserved Reserved (Bit 55) ...
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Table 8. FS7145 REGISTER MAP Address BIT 7 BIT 6 Byte 7 Reserved Reserved (Bit 63) (Bit 62) Must be set Must be set to “0” to “0” Byte 6 Reserved Reserved (Bit 55) (Bit 54) Must be set Must ...
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Table 9. DEVICE CONFIGURATION BITS Name Description REFDSRC Reference divider source [0] = crystal oscillator / [1] = REF pin FBKDSRC Feedback divider source [0] = VCO output / [1] = post divider output SHUT1 Shutdown1 [0] = normal / ...
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Figure 7. Bus Timing Data Figure 8. Data Transfer Sequence http://onsemi.com 14 ...
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PACKAGE DIMENSIONS SSOP 16 CASE 565AE−01 ISSUE O http://onsemi.com 15 ...
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PACKAGE DIMENSIONS SOIC 16 CASE 751BA−01 ISSUE O http://onsemi.com 16 ...
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... ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative FS7140/D ...