ds90ur916q National Semiconductor Corporation, ds90ur916q Datasheet
ds90ur916q
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ds90ur916q Summary of contents
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... Des may be configured to generate Spread Spectrum Clock and Data on its parallel outputs. The DS90UR916Qis offered in a 60-pin LLP package specified over the automotive AEC-Q100 grade 2 tempera- ture range of -40°C to +105°C. Applications Diagram TRI-STATE ® ...
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... LLP, 9.0 X 9.0 X 0.8 mm, 0.5 mm pitch DS90UR916QSQX 60–pin LLP, 9.0 X 9.0 X 0.8 mm, 0.5 mm pitch DS90UR916QSQE 60–pin LLP, 9.0 X 9.0 X 0.8 mm, 0.5 mm pitch Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades defined in the AEC Q100 standard ...
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... DS90UR916Q Pin Diagram Deserializer - DS90UR916Q — Top View 3 30115620 www.national.com ...
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... DS90UR916Q Deserializer Pin Descriptions Pin Name Pin # I/O, Type LVCMOS Parallel Interface R[7:0] 33, 34, 35, I, STRAP, 36, 37, 39, O, LVCMOS 40, 41 G[7:0] 20, 21, 22, I, STRAP, 23, 25, 26, O, LVCMOS 27, 28 B[7:0] 9, 10, 11, I, STRAP, 12, 14, 17, O, LVCMOS 18 LVCMOS Horizontal Sync Output LVCMOS Vertical Sync Output ...
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Pin Name Pin # I/O, Type OS_PCLK 11 [B5] STRAP I, LVCMOS w/ pull-down OS_DATA 14 [B3] STRAP I, LVCMOS w/ pull-down OP_LOW 42 PASS STRAP I, LVCMOS w/ pull-down OSS_SEL 17 [B2] STRAP I, LVCMOS w/ pull-down RFB 18 ...
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Pin Name Pin # I/O, Type NC 1, 15, 16, 30, 31, 45, 46, 60 FPD-Link II Serial Interface RIN LVDS RIN LVDS CMF 51 I, Analog CMLOUTP 52 O, LVDS CMLOUTN 53 O, LVDS Power ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V DDIO LVCMOS I/O Voltage −0.3V to +(VDDIO + 0.3V) ...
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Symbol Parameter V High Level Output Voltage OH V Low Level Output Voltage OL Output Short Circuit Current I OS Output Short Circuit Current I TRI-STATE Output Current OZ LVDS RECEIVER DC SPECIFICATIONS Differential Input Threshold V TH High Voltage ...
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Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t PCLK Output Period RCP t PCLK Output Duty Cycle RDC t LVCMOS CLH Low-to-High Transition Time, t LVCMOS CHL High-to-Low Transition Time, Figure 2 ...
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Recommended Timing for the Serial Control Bus Over 3.3V supply and temperature ranges unless otherwise specified. Symbol Parameter f SCL Clock Frequency SCL t SCL Low Period LOW t SCL High Period HIGH t Hold time for a start or ...
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DC and AC Serial Control Bus Characteristics Over 3.3V supply and temperature ranges unless otherwise specified. Symbol Parameter V Input High Level IH V Input Low Level Voltage IL V Input Hysteresis SDA RiseTime ...
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AC Timing Diagrams and Test Circuits www.national.com FIGURE 1. Checkerboard Data Pattern FIGURE 2. Deserializer LVCMOS Transition Times FIGURE 3. Deserializer Delay – Latency 12 30115632 30115605 30115611 ...
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FIGURE 4. Deserializer Disable Time (OSS_SEL = 0) FIGURE 5. Deserializer PLL Lock Times and PDB TRI-STATE Delay FIGURE 6. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = Off 13 30115613 30115614 30115635 www.national.com ...
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FIGURE 7. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = On www.national.com FIGURE 8. Receiver Input Jitter Tolerance FIGURE 9. BIST PASS Waveform 14 30115634 30115616 30115652 ...
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FIGURE 10. Serial Control Bus Timing Diagram 15 30115636 www.national.com ...
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... H Backwards Compatible GEN1 www.national.com The DS90UR905 / DS90UR916Q chipset can operate in 24- bit color depth (with VS,HS,DE encoded in the DCA bit 18-bit color depth (with VS, HS, DE encoded in DCA or mapped into the high-speed data bits). In 18–bit color appli- cations, the three video signals maybe sent encoded via the DCA bit (restrictions apply) or sent as “ ...
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FIGURE 12. Video Control Signal Filter Waveform DESERIALIZER Functional Description The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal check for the chipset Built In Self Test (BIST) mode. ...
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Adaptive Hi-FRC Dithering The Adaptive FRC Dithering Feature delivers product-differ- entiating image quality. It reduces 24-bit RGB (8 bits per sub- pixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use lower cost ...
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Signal Quality Enhancers Des — Input Equalizer Gain (EQ) The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input. Note this function cannot be seen at the RxIN+/- input but ...
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TABLE 3. SSCG Configuration (LF_MODE = L) — Des Output SSC[3:0] Inputs LF_MODE = L ( MHz) SSC3 SSC2 ...
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... LOCK goes from TRI-STATE to LOW (depending on the value of the OSS_SEL setting). After the DS90UR916Q completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the parallel bus and PCLK outputs ...
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FIGURE 16. Des Outputs with Output State Select Low (OSS_SEL = H) FIGURE 17. Des Outputs with Output State Select High (OSS_SEL = L) www.national.com 22 30115640 30115653 ...
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OSC_SEL[2:0] INPUTS OSC_SEL2 OSC_SEL1 FIGURE 18. Des Outputs with Output State High and PCLK Output Oscillator Option Enabled OP_LOW — Optional The OP_ LOW ...
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FIGURE 19. OP_LOW Auto Set FIGURE 20. OP_LOW Manual Set/Reset 24 30115665 30115666 ...
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... Des detects the BIST mode pattern and command (DCA and DCB code) the RGB and control signal outputs are shut off. DEFAULT Step 2: Place the DS90UR916Q Des in BIST mode by setting LSB the BISTEN = H. The Des is now in the BIST mode and checks LSB 0 the incoming serial payloads for errors ...
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FIGURE 21. BIST Mode Flow Diagram www.national.com BER Calculations It is possible to calculate the approximate Bit Error Rate (BER). The following is required: • Pixel Clock Frequency (MHz) • BIST Duration (seconds) • BIST test Result (PASS) The BER ...
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... Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See 30115641 FIGURE 24. START and STOP Conditions If the Serial Bus is not required, the three pins may be left open (NC). TABLE 9. ID[x] Resistor Value – DS90UR916Q Des Resistor RID* kΩ (5% tol) 0.47 2.7 8 ...
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FIGURE 25. Serial Control Bus — READ FIGURE 26. Serial Control Bus — WRITE 28 30115638 30115639 ...
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TABLE 10. DESERIALIZER — Serial Bus Control Registers PAGE ADD ADD Register Name Bit(s) (dec) (hex Des Config Slave ID R/W Default Function (bin) 7 R/W 0 LFMODE 6 R/W 0 OS_PCLK 5 ...
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PAGE ADD ADD Register Name Bit(s) (dec) (hex Des Features 1 www.national.com R/W Default Function (bin) 7 R/W 0 OP_LOW Release/Set 6 R/W 0 OSS_SEL 5:4 R/W 00 MAP_SEL 3 R/W 0 OP_LOW strap bypass 2:0 R/W ...
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PAGE ADD ADD Register Name Bit(s) (dec) (hex Des Features CMLOUT Config R/W Default Function (bin) 7:5 R/W 000 EQ Gain 4 R Enable 3:0 R/W 0000 SSC 7 R/W 0 ...
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PAGE ADD ADD Register Name Bit(s) (dec) (hex FRC Configuration White Balance Configuration White Balance 255 FF Red LUT White Balance 255 FF Green ...
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Applications Information DISPLAY APPLICATION The DS90UR905/916Q chipset is intended for interface be- tween a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats RGB888 application, 24 ...
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... GPO (General Purpose Output) signals control the PDB and the BISTEN pins. In this application the RRFB pin is tied Low to strobe the data on the falling edge of the PCLK. FIGURE 27. DS90UR916Q Typical Connection Diagram — Pin Control www.national.com The DS90UR916 will most often be used in serial bus control mode as this is required to enable the image enhancement features of the device ...
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... LIVE LINK INSERTION The Ser and Des devices support live pluggable applications. The automatic receiver lock to random data “plug & go” hot insertion capability allows the DS90UR916Q to attain lock to the active data stream during a live insertion event. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS ...
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... USING IMAGE ENHANCEMENT FEATURES The DS90UR916Q offers two FRC dithering blocks and one White Balance lookup table. Depending upon the color depth of the source data, display and LUT contents, these blocks may be independently enabled or disabled in various combi- nations. Refer to Table 11 below for recommendations. ...
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TABLE 12. Alternate Color / Data Mapping — See Text Below 18-bit 18-bit 18-bit 24-bit RGB RGB RGB RGB 0 LSB R0 GP0 0 R1 GP1 MSB ...
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Revision History • 3/28/2011 Updated Ordering Information table www.national.com 38 ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48–pin LLP Package (7 7 0.8 mm, 0.5 mm pitch) 60–pin LLP Package (9 9 0.8 mm, 0.5 mm pitch) NS Package Number SQA48A NS ...
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... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...